| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 33 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
65 def : PatGprGpr<mulhu, MULHU>;
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfoM.td | 33 def MULHU : ALU_rr<0b0000001, 0b011, "mulhu">,
65 def : PatGprGpr<mulhu, MULHU>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 211 case ISD::MULHU: { in trySelect()
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
|
| D | MipsSEISelLowering.cpp | 186 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
197 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
234 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
281 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 211 case ISD::MULHU: { in trySelect()
212 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
|
| D | MipsSEISelLowering.cpp | 186 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
197 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
234 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
281 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
457 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 246 case ISD::MULHU: { in trySelect()
247 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16); in trySelect()
|
| D | MipsSEISelLowering.cpp | 117 setOperationAction(ISD::MULHU, MVT::i32, Custom); in MipsSETargetLowering()
128 setOperationAction(ISD::MULHU, MVT::i64, Custom); in MipsSETargetLowering()
162 setOperationAction(ISD::MULHU, MVT::i32, Legal); in MipsSETargetLowering()
209 setOperationAction(ISD::MULHU, MVT::i64, Legal); in MipsSETargetLowering()
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); in LowerOperation()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 366 case ISD::MULHU: in Select()
371 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; in Select()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 321 MULHU, MULHS, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 441 MULHU, MULHS, enumerator
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 570 MULHU, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 93 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
152 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
1544 case ISD::MULHU: in LowerHvxOperation()
1579 case ISD::MULHU: return LowerHvxMulh(Op, DAG); in LowerHvxOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 338 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
367 setOperationAction(ISD::MULHU, VT, Expand); in AMDGPUTargetLowering()
492 setTargetDAGCombine(ISD::MULHU); in AMDGPUTargetLowering()
1706 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
1721 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
1735 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
1875 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den); in LowerUDIVREM()
1887 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP); in LowerUDIVREM()
1900 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num); in LowerUDIVREM()
3995 case ISD::MULHU: in PerformDAGCombine()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 400 setOperationAction(ISD::MULHU, MVT::i16, Expand); in AMDGPUTargetLowering()
404 setOperationAction(ISD::MULHU, MVT::i64, Expand); in AMDGPUTargetLowering()
433 setOperationAction(ISD::MULHU, VT, Expand); in AMDGPUTargetLowering()
562 setTargetDAGCombine(ISD::MULHU); in AMDGPUTargetLowering()
1835 SDValue Mulhi1 = DAG.getNode(ISD::MULHU, DL, VT, Rcp64, Mullo1); in LowerUDIVREM64()
1850 SDValue Mulhi2 = DAG.getNode(ISD::MULHU, DL, VT, Add1, Mullo2); in LowerUDIVREM64()
1864 SDValue Mulhi3 = DAG.getNode(ISD::MULHU, DL, VT, LHS, Add2); in LowerUDIVREM64()
2006 DAG.getNode(ISD::MULHU, DL, VT, Z, NegYZ)); in LowerUDIVREM()
2009 SDValue Q = DAG.getNode(ISD::MULHU, DL, VT, X, Z); in LowerUDIVREM()
3980 case ISD::MULHU: in PerformDAGCombine()
|
| /external/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 294 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
1188 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_128, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1189 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_256, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1190 X86_INTRINSIC_DATA(avx512_mask_pmulhu_w_512, INTR_TYPE_2OP_MASK, ISD::MULHU, 0),
1900 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2931 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : in BuildUDIV()
2932 isOperationLegalOrCustom(ISD::MULHU, VT)) in BuildUDIV()
2933 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT)); in BuildUDIV()
2987 bool HasMULHU = isOperationLegalOrCustom(ISD::MULHU, HiLoVT); in expandMUL()
3023 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
3073 Hi = DAG.getNode(ISD::MULHU, dl, HiLoVT, LL, RL); in expandMUL()
|
| D | SelectionDAGDumper.cpp | 178 case ISD::MULHU: return "mulhu"; in getOperationName()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 389 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
844 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1054 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86IntrinsicsInfo.h | 389 X86_INTRINSIC_DATA(avx2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
840 X86_INTRINSIC_DATA(avx512_pmulhu_w_512, INTR_TYPE_2OP, ISD::MULHU, 0),
1060 X86_INTRINSIC_DATA(sse2_pmulhu_w, INTR_TYPE_2OP, ISD::MULHU, 0),
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 85 setOperationAction(ISD::MULHU, MVT::i64, Expand); in BPFTargetLowering()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 98 ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS, in WebAssemblyTargetLowering()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 137 setOperationAction(ISD::MULHU, MVT::i8, Expand); in MSP430TargetLowering()
142 setOperationAction(ISD::MULHU, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 117 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
179 setOperationAction(ISD::MULHU, T, Custom); in initializeHVXLowering()
2039 case ISD::MULHU: in LowerHvxOperation()
2079 case ISD::MULHU: return LowerHvxMulh(Op, DAG); in LowerHvxOperation()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 90 setOperationAction(ISD::MULHU, VT, Expand); in BPFTargetLowering()
|