| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVExpandAtomicPseudoInsts.cpp | 259 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
261 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
262 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
272 .addReg(MaskReg); in insertMaskedMerge()
287 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
329 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
427 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
443 .addReg(MaskReg); in expandAtomicMinMaxOp()
486 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
568 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVExpandPseudoInsts.cpp | 276 Register MaskReg, Register ScratchReg) { in insertMaskedMerge() argument
278 assert(OldValReg != MaskReg && "OldValReg and MaskReg must be unique"); in insertMaskedMerge()
279 assert(ScratchReg != MaskReg && "ScratchReg and MaskReg must be unique"); in insertMaskedMerge()
289 .addReg(MaskReg); in insertMaskedMerge()
304 Register MaskReg = MI.getOperand(4).getReg(); in doMaskedAtomicBinOpExpansion() local
346 insertMaskedMerge(TII, DL, LoopMBB, ScratchReg, DestReg, ScratchReg, MaskReg, in doMaskedAtomicBinOpExpansion()
444 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicMinMaxOp() local
460 .addReg(MaskReg); in expandAtomicMinMaxOp()
503 MaskReg, Scratch1Reg); in expandAtomicMinMaxOp()
585 Register MaskReg = MI.getOperand(5).getReg(); in expandAtomicCmpXchg() local
[all …]
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| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 93 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
99 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 101 void emitMask(unsigned AddrReg, unsigned MaskReg, in emitMask() argument
107 MaskInst.addOperand(MCOperand::createReg(MaskReg)); in emitMask()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 213 Register MaskReg = getMRI()->createGenericVirtualRegister(MaskTy); in buildMaskLowPtrBits() local
214 buildConstant(MaskReg, maskTrailingZeros<uint64_t>(NumBits)); in buildMaskLowPtrBits()
215 return buildPtrMask(Res, Op0, MaskReg); in buildMaskLowPtrBits()
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| D | LegalizerHelper.cpp | 6211 Register MaskReg = MI.getOperand(1).getReg(); in lowerSelect() local
6215 LLT MaskTy = MRI.getType(MaskReg); in lowerSelect()
6223 Register MaskElt = MaskReg; in lowerSelect()
6238 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); in lowerSelect()
6239 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); in lowerSelect()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructionSelector.cpp | 2471 Register MaskReg = I.getOperand(2).getReg(); in selectG_PTRMASK() local
2473 LLT MaskTy = MRI->getType(MaskReg); in selectG_PTRMASK()
2477 const RegisterBank *MaskRB = RBI.getRegBank(MaskReg, *MRI, TRI); in selectG_PTRMASK()
2495 !RBI.constrainGenericRegister(MaskReg, *MaskRC, *MRI)) in selectG_PTRMASK()
2506 .addReg(MaskReg); in selectG_PTRMASK()
2524 APInt MaskOnes = KnownBits->getKnownOnes(MaskReg).zextOrSelf(64); in selectG_PTRMASK()
2537 .addReg(MaskReg, 0, AMDGPU::sub0); in selectG_PTRMASK()
2551 .addReg(MaskReg, 0, AMDGPU::sub1); in selectG_PTRMASK()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 8545 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary() local
8604 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
8614 .addReg(TmpDestReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
8616 .addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
9263 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitInstrWithCustomInserter() local
9332 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
9335 .addReg(NewVal2Reg).addReg(MaskReg); in EmitInstrWithCustomInserter()
9337 .addReg(OldVal2Reg).addReg(MaskReg); in EmitInstrWithCustomInserter()
9343 .addReg(TmpDestReg).addReg(MaskReg); in EmitInstrWithCustomInserter()
9353 .addReg(TmpDestReg).addReg(MaskReg); in EmitInstrWithCustomInserter()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10787 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
10861 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
10875 .addReg(MaskReg); in EmitPartwordAtomicBinary()
10876 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
10883 .addReg(MaskReg); in EmitPartwordAtomicBinary()
11601 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
11687 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
11692 .addReg(MaskReg); in EmitInstrWithCustomInserter()
11695 .addReg(MaskReg); in EmitInstrWithCustomInserter()
11703 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 11379 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitPartwordAtomicBinary() local
11453 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitPartwordAtomicBinary()
11467 .addReg(MaskReg); in EmitPartwordAtomicBinary()
11468 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg); in EmitPartwordAtomicBinary()
11475 .addReg(MaskReg); in EmitPartwordAtomicBinary()
12379 Register MaskReg = RegInfo.createVirtualRegister(GPRC); in EmitInstrWithCustomInserter() local
12465 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg) in EmitInstrWithCustomInserter()
12470 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12473 .addReg(MaskReg); in EmitInstrWithCustomInserter()
12481 .addReg(MaskReg); in EmitInstrWithCustomInserter()
[all …]
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 2737 Register MaskReg = I.getOperand(2).getReg(); in select() local
2738 Optional<int64_t> MaskVal = getConstantVRegVal(MaskReg, MRI); in select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4171 Register MaskReg = MIB->getOperand(1).getReg(); in expandPostRAPseudo() local
4179 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) in expandPostRAPseudo()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 4718 Register MaskReg = MIB.getReg(1); in expandPostRAPseudo() local
4726 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState) in expandPostRAPseudo()
|