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Searched refs:NOPs (Results 1 – 25 of 38) sorted by relevance

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/external/mesa3d/src/amd/compiler/
Daco_insert_NOPs.cpp241 void handle_raw_hazard(Program *program, Block *cur_block, int *NOPs, int min_states, Operand op) in handle_raw_hazard() argument
243 if (*NOPs >= min_states) in handle_raw_hazard()
246 *NOPs = MAX2(*NOPs, res); in handle_raw_hazard()
289 aco_ptr<Instruction>& instr, int *NOPs) in handle_smem_clause_hazards() argument
292 if (!*NOPs & (ctx.smem_clause || ctx.smem_write)) { in handle_smem_clause_hazards()
296 *NOPs = 1; in handle_smem_clause_hazards()
300 *NOPs = 1; in handle_smem_clause_hazards()
306 if (!*NOPs && test_bitset_range(ctx.smem_clause_read_write, def.physReg(), def.size())) in handle_smem_clause_hazards()
307 *NOPs = 1; in handle_smem_clause_hazards()
317 int NOPs = 0; in handle_instruction_gfx6() local
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DREADME-ISA.md73 also seems unlikely, since NOPs are apparently needed in a subset of these
182 Any branch that is located at offset 0x3f will be buggy. Just insert some NOPs to make sure no bran…
DREADME.md105 #### Resolve hazards and insert NOPs
/external/llvm/test/MC/X86/
Dx86_long_nop.s8 # Ensure alignment directives also emit sequences of 15-byte NOPs on processors
9 # capable of using long NOPs.
19 # On Silvermont and Lakemont we emit only 7 byte NOPs since longer NOPs
/external/llvm-project/llvm/test/MC/X86/
Dx86_long_nop.s29 # Ensure alignment directives also emit sequences of 10, 11 and 15-byte NOPs on processors
30 # capable of using long NOPs.
53 # On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable.
62 # On Lakemont we emit only 1 byte NOPs since longer NOPs are not supported/legal
/external/llvm-project/llvm/test/MC/X86/AlignedBundling/
Dlong-nop-pad.s16 # To align this group to a bundle end, we need a two 10-byte NOPs and a 7-byte NOP.
26 # To align this group to a bundle end, we need three 10-byte NOPs, and a 1-byte.
/external/llvm/lib/Target/Sparc/
DLeonFeatures.td73 "instructions with NOPs and floating-point store">;
89 "LEON3 erratum fix: Insert NOPs between "
/external/llvm/test/MC/X86/AlignedBundling/
Dlong-nop-pad.s25 # To align this group to a bundle end, we need two 15-byte NOPs, and a 1-byte.
/external/llvm-project/llvm/test/MC/RISCV/
Dalign.s31 # We need to insert N-MinNopSize bytes NOPs and R_RISCV_ALIGN relocation
33 # Linker could satisfy alignment by removing NOPs after linker relaxation.
/external/llvm-project/llvm/lib/Target/Sparc/
DLeonFeatures.td58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DLeonFeatures.td58 "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store"
/external/llvm-project/llvm/test/CodeGen/X86/
Dpatchable-function-entry.ll79 ;; We emit 1-byte NOPs before the function entry, so that with a partial patch,
/external/llvm-project/llvm/test/CodeGen/AVR/
Dbranch-relaxation.ll80 ; There are not enough NOPs to require relaxation.
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dpatchable-function-entry.ll88 ;; When prefix data is used, arbitrarily place NOPs after prefix data.
/external/llvm-project/llvm/lib/Target/X86/
DX86.td355 // If the target can efficiently decode NOPs upto 7-bytes in length.
359 "Target can quickly decode up to 7 byte NOPs">;
360 // If the target can efficiently decode NOPs upto 11-bytes in length.
364 "Target can quickly decode up to 11 byte NOPs">;
365 // If the target can efficiently decode NOPs upto 15-bytes in length.
369 "Target can quickly decode up to 15 byte NOPs">;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86.td332 // If the target can efficiently decode NOPs upto 11-bytes in length.
336 "Target can quickly decode up to 11 byte NOPs">;
337 // If the target can efficiently decode NOPs upto 15-bytes in length.
341 "Target can quickly decode up to 15 byte NOPs">;
/external/llvm/include/llvm/Target/
DTargetOpcodes.def107 /// constant address, followed by a series of NOPs. It is intended to
/external/XNNPACK/src/f32-gemm/
D4x8-aarch64-neonfma-cortex-a55.S.in202 // NOPs to ensure 4 cycle LDR lands on next LDR
305 // NOPs to ensure 4 cycle LDR lands on next LDR
D4x8-aarch64-neonfma-cortex-a53.S.in202 // NOPs to ensure 4 cycle LDR lands on next LDR
314 // NOPs to ensure 4 cycle LDR lands on next LDR
/external/llvm-project/llvm/docs/HistoricalNotes/
D2003-06-25-Reoptimizer1.txt71 We turn off llvm_first_trigger() calls with NOPs, but this would hide
/external/llvm/docs/HistoricalNotes/
D2003-06-25-Reoptimizer1.txt71 We turn off llvm_first_trigger() calls with NOPs, but this would hide
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dbranch-relaxation.ll363 ; These NOPs prevent tail-duplication-based outlining
/external/llvm-project/clang/include/clang/Basic/
DCodeGenOptions.def130 VALUE_CODEGENOPT(PatchableFunctionEntryCount , 32, 0) ///< Number of NOPs at function entry
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DTargetOpcodes.def118 /// constant address, followed by a series of NOPs. It is intended to
/external/llvm-project/llvm/include/llvm/Support/
DTargetOpcodes.def125 /// constant address, followed by a series of NOPs. It is intended to

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