| /external/capstone/arch/M680X/ |
| D | insn_props.inc | 4 #define NOR M680X_REG_INVALID
7 { NOG, uuuu, NOR, NOR, false, false }, // INVLD
11 { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADC
12 { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADCA
13 { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADCB
14 { NOG, mrrr, M680X_REG_D, NOR, true, false }, // ADCD
15 { NOG, rmmm, NOR, NOR, true, false }, // ADCR
16 { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADD
17 { NOG, mrrr, M680X_REG_A, NOR, true, false }, // ADDA
18 { NOG, mrrr, M680X_REG_B, NOR, true, false }, // ADDB
[all …]
|
| /external/llvm-project/llvm/test/MC/Mips/ |
| D | instalias-imm-expanding.s | 344 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
347 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
351 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
354 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
358 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
361 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
365 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
368 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
372 # MIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
375 # MICROMIPS-NEXT: # <MCInst #{{[0-9]+}} NOR
[all …]
|
| /external/arm-trusted-firmware/fdts/ |
| D | corstone700_fvp.dts | 15 * Intel StrataFlash J3 NOR flash: 2 x 16-bit interleaved components
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 445 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes) in expandAtomicBinOpSubword()
639 unsigned NOR = 0; in expandAtomicBinOp() local
666 NOR = Mips::NOR; in expandAtomicBinOp()
689 NOR = Mips::NOR64; in expandAtomicBinOp()
787 assert(AND && NOR && in expandAtomicBinOp()
790 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch); in expandAtomicBinOp()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsExpandPseudo.cpp | 445 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes) in expandAtomicBinOpSubword()
639 unsigned NOR = 0; in expandAtomicBinOp() local
666 NOR = Mips::NOR; in expandAtomicBinOp()
689 NOR = Mips::NOR64; in expandAtomicBinOp()
787 assert(AND && NOR && in expandAtomicBinOp()
790 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch); in expandAtomicBinOp()
|
| /external/arm-trusted-firmware/docs/plat/marvell/armada/misc/ |
| D | mvebu-amb.rst | 7 transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR).
|
| D | mvebu-iob.rst | 39 - **0x6** = RUNIT (NOR/SPI/BootRoom)
|
| /external/libutf/ |
| D | NOTICE | 10 * WARRANTY. IN PARTICULAR, NEITHER THE AUTHORS NOR LUCENT TECHNOLOGIES MAKE ANY
|
| /external/llvm-project/llvm/test/CodeGen/SystemZ/ |
| D | not-01.ll | 65 ; NOR 32-bit.
75 ; NOR 64-bit.
|
| /external/webrtc/modules/third_party/fft/ |
| D | LICENSE | 12 * IMPLIED WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR QUEEN'S
|
| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | bitwise.mir | 224 ; MIPS32: [[NOR:%[0-9]+]]:gpr32 = NOR [[COPY]], $zero
225 ; MIPS32: $v0 = COPY [[NOR]]
|
| /external/vboot_reference/tests/testkeys/ |
| D | key_rsa8192.pem | 53 8kCDozA78x9wRjKbMhh4RZJIyuc9X+e7gRBqbpiW8hvZXQxMAtyHjidR1GiM+NOR
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 125 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
127 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst))); in emit_single_op()
164 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
306 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
|
| D | sljitNativeMIPS_64.c | 216 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
218 FAIL_IF(push_inst(compiler, NOR | S(src2) | T(src2) | D(dst), DR(dst))); in emit_single_op()
255 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
397 FAIL_IF(push_inst(compiler, NOR | S(src1) | T(src1) | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
|
| D | sljitNativePPC_32.c | 87 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2)); in emit_single_op()
|
| /external/arm-trusted-firmware/docs/plat/ |
| D | ls1043a.rst | 18 * 128 Mbyte NOR flash single-chip memory
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 254 case Mips::NOR: in printAlias()
|
| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsInstPrinter.cpp | 254 case Mips::NOR: in printAlias()
|
| /external/python/cpython2/PC/VS7.1/ |
| D | Uninstal.wse | 350 Value=%_WISE_%\LANGUAGE\UNWISE.NOR
358 Source=%_WISE_%\LANGUAGE\UNWISE.NOR
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| D | MipsInstPrinter.cpp | 259 case Mips::NOR: in printAlias()
|
| /external/mesa3d/docs/gallium/cso/ |
| D | blend.rst | 38 * ``NOR``: :math:`\lnot(s \lor d)`
|
| /external/arm-trusted-firmware/docs/plat/marvell/armada/ |
| D | build.rst | 187 - SPINOR - SPI NOR flash boot
258 the image boot from SPI NOR flash partition 0, and the image is non trusted in WTP, the command
|
| /external/arm-trusted-firmware/docs/plat/arm/fvp/ |
| D | index.rst | 197 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
390 - The Firmware Image Package is loaded at the start of NOR FLASH0.
|
| /external/selinux/mcstrans/share/examples/nato/setrans.d/ |
| D | eyes-only.conf | 493 ~c366=NOR # Norway
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1114 unsigned LL, SC, AND, NOR, ZERO, BEQ; in emitAtomicBinary() local
1130 NOR = Mips::NOR; in emitAtomicBinary()
1137 NOR = Mips::NOR64; in emitAtomicBinary()
1181 BuildMI(BB, DL, TII->get(NOR), StoreVal).addReg(ZERO).addReg(AndRes); in emitAtomicBinary()
1323 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicBinaryPartword()
1352 BuildMI(BB, DL, TII->get(Mips::NOR), BinOpRes) in emitAtomicBinaryPartword()
1586 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); in emitAtomicCmpSwapPartword()
|