Searched refs:OP_QUADON (Results 1 – 13 of 13) sorted by relevance
/external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
D | nv50_ir_target_gm107.cpp | 262 case OP_QUADON: in getLatency()
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D | nv50_ir_target_nv50.cpp | 129 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP, in initOpInfo() 134 OP_CALL, OP_PREBREAK, OP_PRERET, OP_QUADON, OP_QUADPOP, OP_JOINAT, in initOpInfo()
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D | nv50_ir_target_nvc0.cpp | 212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP, in initOpInfo() 218 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP, in initOpInfo()
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D | nv50_ir_build_util.h | 266 op == OP_QUADON || op == OP_QUADPOP || in mkOp()
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D | nv50_ir_lowering_gm107.cpp | 123 bld.mkOp(OP_QUADON, TYPE_NONE, NULL); in handleManualTXD()
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D | nv50_ir_lowering_gv100.cpp | 290 case OP_QUADON: in visit()
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D | nv50_ir_emit_nv50.cpp | 2012 case OP_QUADON: in emitInstruction() 2152 insn->op == OP_QUADON || in trySetExitModifier()
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D | nv50_ir.h | 151 OP_QUADON, enumerator
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D | nv50_ir_emit_gk110.cpp | 1528 case OP_QUADON: code[1] = 0x1b800000; mask = 0; break; in emitFlow() 2680 case OP_QUADON: in emitInstruction()
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D | nv50_ir_emit_nvc0.cpp | 1475 case OP_QUADON: code[1] = 0xc0000000; mask = 0; break; in emitFlow() 2874 case OP_QUADON: in emitInstruction()
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D | nv50_ir_emit_gm107.cpp | 3456 case OP_QUADON: in emitInstruction() 3995 if (insn->op == OP_QUADON || in setDelay()
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D | nv50_ir_lowering_nv50.cpp | 960 bld.mkOp(OP_QUADON, TYPE_NONE, NULL); in handleTXD()
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D | nv50_ir_lowering_nvc0.cpp | 1227 bld.mkOp(OP_QUADON, TYPE_NONE, NULL); in handleManualTXD()
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