| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1739 Register OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1740 if (OpReg == 0) return false; in X86SelectBranch()
1743 .addReg(OpReg).addImm(1); in X86SelectBranch()
1774 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1775 if (OpReg == 0) return false; in X86SelectBranch()
1778 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1779 unsigned KOpReg = OpReg; in X86SelectBranch()
1780 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1782 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1784 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Op0IsKill=*/true, in X86SelectBranch()
[all …]
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| D | X86SpeculativeLoadHardening.cpp | 1661 Register OpReg = Op->getReg(); in hardenLoadAddr() local
1662 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
1700 .addReg(OpReg); in hardenLoadAddr()
1731 .addReg(OpReg); in hardenLoadAddr()
1744 .addReg(OpReg); in hardenLoadAddr()
1753 .addReg(OpReg) in hardenLoadAddr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1723 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1724 if (OpReg == 0) return false; in X86SelectBranch()
1727 .addReg(OpReg).addImm(1); in X86SelectBranch()
1758 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1759 if (OpReg == 0) return false; in X86SelectBranch()
1762 if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { in X86SelectBranch()
1763 unsigned KOpReg = OpReg; in X86SelectBranch()
1764 OpReg = createResultReg(&X86::GR32RegClass); in X86SelectBranch()
1766 TII.get(TargetOpcode::COPY), OpReg) in X86SelectBranch()
1768 OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, /*Kill=*/true, in X86SelectBranch()
[all …]
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| D | X86SpeculativeLoadHardening.cpp | 2034 Register OpReg = Op->getReg(); in hardenLoadAddr() local
2035 auto *OpRC = MRI->getRegClass(OpReg); in hardenLoadAddr()
2073 .addReg(OpReg); in hardenLoadAddr()
2104 .addReg(OpReg); in hardenLoadAddr()
2117 .addReg(OpReg); in hardenLoadAddr()
2126 .addReg(OpReg) in hardenLoadAddr()
|
| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1654 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1655 if (OpReg == 0) return false; in X86SelectBranch()
1657 .addReg(OpReg).addImm(1); in X86SelectBranch()
1690 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1691 if (OpReg == 0) return false; in X86SelectBranch()
1694 .addReg(OpReg).addImm(1); in X86SelectBranch()
1702 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
1708 case Instruction::LShr: OpReg = X86::SHR8rCL; break; in X86SelectShift()
1709 case Instruction::AShr: OpReg = X86::SAR8rCL; break; in X86SelectShift()
1710 case Instruction::Shl: OpReg = X86::SHL8rCL; break; in X86SelectShift()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 306 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
308 if (!TRI->isVirtualRegister(OpReg)) in optimizeSDPattern()
311 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 298 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
300 if (!Register::isVirtualRegister(OpReg)) in optimizeSDPattern()
303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
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| D | ARMInstructionSelector.cpp | 1043 Register OpReg = I.getOperand(2).getReg(); in select() local
1044 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 298 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
300 if (!Register::isVirtualRegister(OpReg)) in optimizeSDPattern()
303 MachineInstr *Def = MRI->getVRegDef(OpReg); in optimizeSDPattern()
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| D | ARMInstructionSelector.cpp | 1045 Register OpReg = I.getOperand(2).getReg(); in select() local
1046 unsigned Size = MRI.getType(OpReg).getSizeInBits(); in select()
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| D | ARMFastISel.cpp | 1276 unsigned OpReg = getRegForValue(TI->getOperand(0)); in SelectBranch() local
1277 OpReg = constrainOperandRegClass(TII.get(TstOpc), OpReg, 0); in SelectBranch()
1280 .addReg(OpReg).addImm(1)); in SelectBranch()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 163 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
166 if (encodeOperand(OpReg, Reg, WantedRegSet) != true) in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
174 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister() argument
179 return encodeRegister(OpReg, WantFPRegs, RegName, InstName); in encodeFPRegister()
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| D | IceAssemblerARM32.cpp | 540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister() argument
543 if (encodeOperand(OpReg, Reg, WantedRegSet) != EncodedAsRegister) in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister() argument
551 return encodeRegister(OpReg, WantGPRegs, RegName, InstName); in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister() argument
556 return encodeRegister(OpReg, WantSRegs, RegName, InstName); in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister() argument
561 return encodeRegister(OpReg, WantDRegs, RegName, InstName); in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister() argument
566 return encodeRegister(OpReg, WantQRegs, RegName, InstName); in encodeQRegister()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 853 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
854 LLT OpTy = MRI.getType(OpReg); in executeInWaterfallLoop()
856 const RegisterBank *OpBank = getRegBank(OpReg, MRI, *TRI); in executeInWaterfallLoop()
860 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
861 MRI.setRegBank(OpReg, AMDGPU::VGPRRegBank); in executeInWaterfallLoop()
874 constrainGenericRegister(OpReg, AMDGPU::VGPR_32RegClass, MRI); in executeInWaterfallLoop()
878 .addReg(OpReg); in executeInWaterfallLoop()
889 .addReg(OpReg); in executeInWaterfallLoop()
921 auto Unmerge = B.buildUnmerge(UnmergeTy, OpReg); in executeInWaterfallLoop()
3279 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
[all …]
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| D | AMDGPUInstructionSelector.cpp | 2194 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2205 BuildMI(*BB, &MI, DL, TII.get(Opc), OpReg) in selectG_FNEG()
2211 .addReg(OpReg) in selectG_FNEG()
2231 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
2246 BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_AND_B32), OpReg) in selectG_FABS()
2252 .addReg(OpReg) in selectG_FABS()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1478 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in selectFNeg() local
1479 if (!OpReg) in selectFNeg()
1486 OpReg, OpRegIsKill); in selectFNeg()
1501 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3515 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
3517 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
3524 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarExtract()
3582 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
3584 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
3592 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
3595 DstRegs.push_back(OpReg); in narrowScalarInsert()
3614 Register SegReg = OpReg; in narrowScalarInsert()
3618 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); in narrowScalarInsert()
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1778 Register OpReg = getRegForValue(In); in selectFNeg() local
1779 if (!OpReg) in selectFNeg()
1786 OpReg, OpRegIsKill); in selectFNeg()
1801 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1711 unsigned OpReg = getRegForValue(In); in selectFNeg() local
1712 if (!OpReg) in selectFNeg()
1719 OpReg, OpRegIsKill); in selectFNeg()
1734 ISD::BITCAST, OpReg, OpRegIsKill); in selectFNeg()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3129 Register OpReg = MI.getOperand(1).getReg(); in lower() local
3133 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); in lower()
3134 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); in lower()
4501 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
4503 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarExtract()
4510 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarExtract()
4570 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
4572 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalarInsert()
4580 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { in narrowScalarInsert()
4583 DstRegs.push_back(OpReg); in narrowScalarInsert()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1950 Register OpReg = MO.getReg(); in clearRegisterKills() local
1951 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 2013 unsigned OpReg = MO.getReg(); in clearRegisterKills() local
2014 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1858 Register OpReg = MO.getReg(); in clearRegisterKills() local
1859 if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) in clearRegisterKills()
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4541 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4558 TOut.emitRRR(OpCode, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSge()
4678 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
4695 TOut.emitRRR(OpCode, DstReg, OpReg, SrcReg, IDLoc, STI); in expandSle()
5369 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5373 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSeq()
5374 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI); in expandSeq()
5379 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg; in expandSeq()
5450 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
5454 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) { in expandSne()
[all …]
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT() local
178 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits()); in getRegOperandVectorVT()
|