| /external/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 109 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
111 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
114 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
150 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
153 << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
154 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop "); in Decode_10110001_0000iiii()
155 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
156 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
179 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
180 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
[all …]
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| /external/llvm-project/llvm/tools/llvm-readobj/ |
| D | ARMEHABIPrinter.h | 112 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii() local
114 uint16_t GPRMask = (Opcode1 << 4) | ((Opcode0 & 0x0f) << 12); in Decode_1000iiii_iiiiiiii()
117 Opcode0, Opcode1, GPRMask ? "pop " : "refuse to unwind"); in Decode_1000iiii_iiiiiiii()
159 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110001_0000iiii() local
162 << format("0x%02X 0x%02X ; %s", Opcode0, Opcode1, in Decode_10110001_0000iiii()
163 ((Opcode1 & 0xf0) || Opcode1 == 0x00) ? "spare" : "pop "); in Decode_10110001_0000iiii()
164 if (((Opcode1 & 0xf0) == 0x00) && Opcode1) in Decode_10110001_0000iiii()
165 PrintGPR((Opcode1 & 0x0f)); in Decode_10110001_0000iiii()
188 uint8_t Opcode1 = Opcodes[OI++ ^ 3]; in Decode_10110011_sssscccc() local
189 SW.startLine() << format("0x%02X 0x%02X ; pop ", Opcode0, Opcode1); in Decode_10110011_sssscccc()
[all …]
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1086 IValueT Opcode1 = 0; in emitInsertExtractInt() local
1096 Opcode1 = B1 | mask(Index, 2, 1); in emitInsertExtractInt()
1102 Opcode1 = mask(Index, 1, 1); in emitInsertExtractInt()
1108 Opcode1 = mask(Index, 0, 1); in emitInsertExtractInt()
1113 (Opcode1 << 21) | in emitInsertExtractInt()
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 137 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
140 (cast<Instruction>(V)->getOpcode() == Opcode1 || in isReassociableOp()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 156 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
160 (I->getOpcode() == Opcode1 || I->getOpcode() == Opcode2)) in isReassociableOp()
|
| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 157 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode1, in isReassociableOp() argument
161 (I->getOpcode() == Opcode1 || I->getOpcode() == Opcode2)) in isReassociableOp()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2338 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
2347 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2599 int64_t Offset1, unsigned Opcode1, int FI2, in shouldClusterFI() argument
2608 int Scale1 = AArch64InstrInfo::getMemScale(Opcode1); in shouldClusterFI()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 34539 unsigned Opcode1 = BC1.getOpcode(); in combineTargetShuffle() local
34540 if (Opcode0 == Opcode1 && VT0 == VT1 && in combineTargetShuffle()
34684 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
34685 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
34686 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
34690 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
34697 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 35882 unsigned Opcode1 = BC1.getOpcode(); in canonicalizeShuffleMaskWithHorizOp() local
35883 if (Opcode0 != Opcode1 || VT0 != VT1 || VT0.getSizeInBits() != RootSizeInBits) in canonicalizeShuffleMaskWithHorizOp()
37026 unsigned Opcode1 = N1.getOpcode(); in combineTargetShuffle() local
37027 if (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL || Opcode1 == ISD::FSUB || in combineTargetShuffle()
37028 Opcode1 == ISD::FDIV) { in combineTargetShuffle()
37032 (N11 == N0 && (Opcode1 == ISD::FADD || Opcode1 == ISD::FMUL))) { in combineTargetShuffle()
37039 SDValue Scl = DAG.getNode(Opcode1, DL, SVT, N10, N11); in combineTargetShuffle()
|