| /external/tensorflow/tensorflow/compiler/mlir/lite/quantization/ |
| D | quantization_traits.h | 119 template <int QuantDim, int OperandIndex = 1>
125 AffineOpCoefficient<QuantDim, OperandIndex>::Impl> {
127 static int GetCoefficientOperandIndex() { return OperandIndex; } in GetCoefficientOperandIndex()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 50 unsigned OperandIndex; member
53 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 67 unsigned OperandIndex; member
70 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 67 unsigned OperandIndex; member
70 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
71 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
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| /external/llvm/utils/TableGen/ |
| D | X86DisassemblerTables.cpp | 637 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
638 ++OperandIndex) { in emitInstructionInfo()
640 .operands[OperandIndex].encoding; in emitInstructionInfo()
642 .operands[OperandIndex].type; in emitInstructionInfo()
670 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
671 ++OperandIndex) { in emitInstructionInfo()
673 .operands[OperandIndex].encoding; in emitInstructionInfo()
675 .operands[OperandIndex].type; in emitInstructionInfo()
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| /external/llvm/lib/Target/Sparc/ |
| D | LeonPasses.cpp | 30 int OperandIndex) { in GetRegIndexForOperand() argument
32 if (OperandIndex == LAST_OPERAND) { in GetRegIndexForOperand()
33 OperandIndex = MI.getNumOperands() - 1; in GetRegIndexForOperand()
36 if (MI.getNumOperands() > (unsigned)OperandIndex && in GetRegIndexForOperand()
37 MI.getOperand(OperandIndex).isReg()) { in GetRegIndexForOperand()
38 return (int)MI.getOperand(OperandIndex).getReg(); in GetRegIndexForOperand()
463 for (unsigned OperandIndex = 0; OperandIndex < NumOperands; in runOnMachineFunction() local
464 OperandIndex++) { in runOnMachineFunction()
465 MachineOperand &MO = MI.getOperand(OperandIndex); in runOnMachineFunction()
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| D | LeonPasses.h | 38 int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex);
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstCombineIntrinsic.cpp | 109 for (unsigned OperandIndex = ImageDimIntr->GradientStart; in simplifyAMDGCNImageIntrinsic() local
110 OperandIndex < ImageDimIntr->VAddrEnd; OperandIndex++) { in simplifyAMDGCNImageIntrinsic()
111 Value *Coord = II.getOperand(OperandIndex); in simplifyAMDGCNImageIntrinsic()
114 if (OperandIndex < ImageDimIntr->CoordStart || in simplifyAMDGCNImageIntrinsic()
123 assert(OperandIndex == ImageDimIntr->GradientStart || in simplifyAMDGCNImageIntrinsic()
153 for (unsigned OperandIndex = ImageDimIntr->GradientStart; in simplifyAMDGCNImageIntrinsic() local
154 OperandIndex < EndIndex; OperandIndex++) { in simplifyAMDGCNImageIntrinsic()
155 Args[OperandIndex] = in simplifyAMDGCNImageIntrinsic()
156 convertTo16Bit(*II.getOperand(OperandIndex), IC.Builder); in simplifyAMDGCNImageIntrinsic()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | X86DisassemblerTables.cpp | 826 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
827 ++OperandIndex) { in emitInstructionInfo()
829 .operands[OperandIndex].encoding; in emitInstructionInfo()
831 .operands[OperandIndex].type; in emitInstructionInfo()
859 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; in emitInstructionInfo() local
860 ++OperandIndex) { in emitInstructionInfo()
862 .operands[OperandIndex].encoding; in emitInstructionInfo()
864 .operands[OperandIndex].type; in emitInstructionInfo()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | LeonPasses.h | 36 int GetRegIndexForOperand(MachineInstr &MI, int OperandIndex);
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| /external/llvm-project/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 221 unsigned OperandIndex) { in getMissedOperand() argument
227 Result.MissedOperand.Index = OperandIndex; in getMissedOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/MCParser/ |
| D | MCTargetAsmParser.h | 222 unsigned OperandIndex) { in getMissedOperand() argument
228 Result.MissedOperand.Index = OperandIndex; in getMissedOperand()
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| /external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| D | MCInstrDescView.cpp | 285 for (auto OperandIndex : Var.TiedOperands) { in dump() local
288 Stream << "Op" << OperandIndex; in dump()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | VPlanSLP.cpp | 161 unsigned OperandIndex) { in getOperands() argument
165 Operands.push_back(U->getOperand(OperandIndex)); in getOperands()
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| /external/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | VPlanSLP.cpp | 161 unsigned OperandIndex) { in getOperands() argument
166 Operands.push_back(U->getOperand(OperandIndex)); in getOperands()
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| D | SLPVectorizer.cpp | 7303 unsigned OperandIndex = OperandOffset; in getOperandIndex() local
7307 OperandIndex *= VT->getNumElements(); in getOperandIndex()
7308 OperandIndex += CI->getZExtValue(); in getOperandIndex()
7309 return OperandIndex; in getOperandIndex()
7318 OperandIndex *= ST->getNumElements(); in getOperandIndex()
7321 OperandIndex *= AT->getNumElements(); in getOperandIndex()
7326 OperandIndex += Index; in getOperandIndex()
7328 return OperandIndex; in getOperandIndex()
7338 Optional<unsigned> OperandIndex = in findBuildAggregate_rec() local
7340 if (!OperandIndex) in findBuildAggregate_rec()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 448 I->OperandIndex)); in addVRegDefDeps()
449 ST.adjustSchedDependency(SU, OperIdx, UseSU, I->OperandIndex, Dep); in addVRegDefDeps()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 175 unsigned OperandIndex) { in getRegOperandVectorVT() argument
176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 216 unsigned OperandIndex) { in getRegOperandNumElts() argument
217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
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| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 250 unsigned OperandIndex) { in getRegOperandNumElts() argument
251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 446 I->OperandIndex)); in addVRegDefDeps()
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| /external/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 1051 unsigned OperandIndex; in rewriteInputConstraintReferences() local
1052 if (!OperandStr.getAsInteger(10, OperandIndex)) { in rewriteInputConstraintReferences()
1053 if (OperandIndex >= FirstIn) in rewriteInputConstraintReferences()
1054 OperandIndex += NumNewOuts; in rewriteInputConstraintReferences()
1055 OS << OperandIndex; in rewriteInputConstraintReferences()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 463 I->OperandIndex)); in addVRegDefDeps()
|
| /external/llvm-project/clang/lib/CodeGen/ |
| D | TargetInfo.cpp | 1283 unsigned OperandIndex; in rewriteInputConstraintReferences() local
1284 if (!OperandStr.getAsInteger(10, OperandIndex)) { in rewriteInputConstraintReferences()
1285 if (OperandIndex >= FirstIn) in rewriteInputConstraintReferences()
1286 OperandIndex += NumNewOuts; in rewriteInputConstraintReferences()
1287 OS << OperandIndex; in rewriteInputConstraintReferences()
|