| /external/llvm/lib/CodeGen/ |
| D | InlineSpiller.cpp | 89 bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
104 void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
1080 bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, in isSpillCandBB() argument
1083 LiveInterval &OrigLI = LIS.getInterval(OrigReg); in isSpillCandBB()
1089 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
1090 assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI && in isSpillCandBB()
1229 unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills, in runHoistSpills() argument
1304 if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg)) in runHoistSpills()
1384 unsigned OrigReg = SlotToOrigReg[Slot]; in hoistAllSpills() local
1385 LiveInterval &OrigLI = LIS.getInterval(OrigReg); in hoistAllSpills()
[all …]
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| D | TailDuplicator.cpp | 287 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, in addSSAUpdateEntry() argument
290 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
296 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
297 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
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| D | SplitKit.cpp | 316 unsigned OrigReg = VRM.getOriginal(CurLI->reg); in isOriginalEndpoint() local
317 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | TailDuplicator.h | 60 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TailDuplicator.h | 98 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 555 Register OrigReg = U.getReg(); in colorChain() local
556 U.setReg(Substs[OrigReg]); in colorChain()
560 ToErase.push_back(OrigReg); in colorChain()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 555 Register OrigReg = U.getReg(); in colorChain() local
556 U.setReg(Substs[OrigReg]); in colorChain()
560 ToErase.push_back(OrigReg); in colorChain()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 570 unsigned OrigReg = U.getReg(); in colorChain() local
571 U.setReg(Substs[OrigReg]); in colorChain()
575 ToErase.push_back(OrigReg); in colorChain()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TailDuplicator.h | 101 void addSSAUpdateEntry(Register OrigReg, Register NewReg,
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TailDuplicator.cpp | 329 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, in addSSAUpdateEntry() argument
332 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
338 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
339 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
|
| D | InlineSpiller.cpp | 1173 unsigned OrigReg = OrigLI.reg; in isSpillCandBB() local
1179 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TailDuplicator.cpp | 331 void TailDuplicator::addSSAUpdateEntry(Register OrigReg, Register NewReg, in addSSAUpdateEntry() argument
334 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
340 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
341 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
|
| D | InlineSpiller.cpp | 1203 Register OrigReg = OrigLI.reg(); in isSpillCandBB() local
1209 SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
|
| D | SplitKit.cpp | 336 unsigned OrigReg = VRM.getOriginal(CurLI->reg()); in isOriginalEndpoint() local
337 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 468 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
470 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
476 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 468 Register OrigReg = MO.getReg(); in applyDefaultMapping() local
470 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
476 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 3623 const SCEV *OrigReg; member
3626 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
3635 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
3682 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
3685 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
3687 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
3689 DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg << '\n'); in GenerateCrossUseConstantOffsets()
3710 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
3725 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
3727 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 4083 const SCEV *OrigReg; member
4086 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4096 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4145 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4148 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
4150 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4152 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg in GenerateCrossUseConstantOffsets()
4179 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4194 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4196 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 4078 const SCEV *OrigReg; member
4081 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
4091 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4140 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4143 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
4145 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4147 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg in GenerateCrossUseConstantOffsets()
4174 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4189 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4191 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 658 Register OrigReg = VRM->getPhys(C.Reg); in tryReassign() local
678 LRM->assign(LI, OrigReg); in tryReassign()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 725 MCRegister OrigReg = VRM->getPhys(C.Reg); in tryReassign() local
745 LRM->assign(LI, OrigReg); in tryReassign()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 162 Register widenWithUnmerge(LLT WideTy, Register OrigReg);
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1078 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1084 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1089 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1091 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1093 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1103 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1346 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1352 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1357 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1359 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1361 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1371 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
|
| /external/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1663 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1674 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1676 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1678 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1688 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
|