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Searched refs:PLAT_PERCPU_BAKERY_LOCK_SIZE (Results 1 – 8 of 8) sorted by relevance

/external/arm-trusted-firmware/lib/locks/bakery/
Dbakery_lock_normal.c38 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
47 CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
49 #define PERCPU_BAKERY_LOCK_SIZE (PLAT_PERCPU_BAKERY_LOCK_SIZE)
/external/arm-trusted-firmware/include/common/
Dbl_common.ld.h130 #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
133 (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), \
/external/arm-trusted-firmware/plat/layerscape/board/ls1043/include/
Dls_def.h105 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) macro
/external/arm-trusted-firmware/plat/qti/sc7180/inc/
Dplatform_def.h99 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/scat/
Dbl31.scat197 /* PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements */
198 ScatterAssert(__PER_CPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE)
/external/arm-trusted-firmware/include/plat/arm/common/
Darm_def.h563 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) macro
/external/arm-trusted-firmware/docs/design/
Dfirmware-design.rst2233 optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
/external/arm-trusted-firmware/docs/getting_started/
Dporting-guide.rst1918 #define : PLAT_PERCPU_BAKERY_LOCK_SIZE [optional]