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Searched refs:PMI_ADDR_LANE0 (Results 1 – 1 of 1) sorted by relevance

/external/arm-trusted-firmware/plat/brcm/board/stingray/src/
Dsr_paxb_phy.c36 #define PMI_ADDR_LANE0(addr) ((0x1 << 27) | (addr)) macro
526 paxb_pmi_read(core_idx, PMI_ADDR_LANE0(PMI_PLL_CTRL_4), &rdata); in paxb_serdes_gate_clock()
567 PMI_ADDR_LANE0(UC_A_AHB_STAT0), in paxb_gen3_serdes_init()
599 paxb_pmi_read(core_idx, PMI_ADDR_LANE0(DSC_UC_CTRL), in paxb_gen3_serdes_init()
602 paxb_pmi_write(core_idx, PMI_ADDR_LANE0(DSC_UC_CTRL), in paxb_gen3_serdes_init()
622 PMI_ADDR_LANE0(UC_VERSION_NUM), in paxb_gen3_serdes_init()
625 PMI_ADDR_LANE0(DSC_SM_CTL22), in paxb_gen3_serdes_init()