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Searched refs:PMUGRF_BASE (Results 1 – 9 of 9) sorted by relevance

/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pwm/
Dpwm.c52 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX); in disable_pwms()
58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in disable_pwms()
61 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX); in disable_pwms()
67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in disable_pwms()
100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val); in enable_pwms()
107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val); in enable_pwms()
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/pmu/
Dpmu.c584 mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON0); in pvtm_32k_config()
586 mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_CON1); in pvtm_32k_config()
588 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
591 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
594 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON1, PVTM_CALC_CNT); in pvtm_32k_config()
597 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
604 while (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) < 30) in pvtm_32k_config()
608 while (!(mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST0) & 0x1)) in pvtm_32k_config()
612 (mmio_read_32(PMUGRF_BASE + PMUGRF_PVTM_ST1) * 24000 + in pvtm_32k_config()
625 mmio_write_32(PMUGRF_BASE + PMUGRF_PVTM_CON0, in pvtm_32k_config()
[all …]
/external/arm-trusted-firmware/plat/rockchip/px30/drivers/soc/
Dsoc.c95 tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3)); in soc_reset_config_all()
97 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp); in soc_reset_config_all()
124 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(2), in px30_soc_reset_config()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/
Ddram.c19 os_reg2_val = mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)); in dram_init()
Ddfs.c1745 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in exit_low_power()
1783 channel_mask = (mmio_read_32(PMUGRF_BASE + PMUGRF_OSREG(2)) >> 28) & in resume_low_power()
/external/arm-trusted-firmware/plat/rockchip/px30/
Dpx30_def.h24 #define PMUGRF_BASE 0xff010000 macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/include/shared/
Daddressmap_shared.h27 #define PMUGRF_BASE (MMIO_BASE + 0x07320000) macro
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/gpio/
Drk3399_gpio.c172 val = mmio_read_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + in get_pull()
231 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P + in set_pull()
/external/arm-trusted-firmware/plat/rockchip/rk3399/drivers/pmu/
Dpmu.c891 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K); in sys_slp_config()
892 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */ in sys_slp_config()
1549 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX, in rockchip_soc_system_off()
1617 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE); in plat_rockchip_pmu_init()