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Searched refs:PRE_INC (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h809 PRE_INC, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h987 PRE_INC, enumerator
DBasicTTIImpl.h179 return ISD::PRE_INC; in getISDIndexedMode()
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1212 enum MemIndexedMode { UNINDEXED = 0, PRE_INC, PRE_DEC, POST_INC, POST_DEC }; enumerator
DBasicTTIImpl.h176 return ISD::PRE_INC; in getISDIndexedMode()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGAddressAnalysis.cpp178 if (N->getAddressingMode() == ISD::PRE_INC) { in matchLSNode()
DSelectionDAGDumper.cpp457 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGAddressAnalysis.cpp189 if (N->getAddressingMode() == ISD::PRE_INC) { in matchLSNode()
DSelectionDAGDumper.cpp484 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp793 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
829 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
849 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
928 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1332 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1401 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset()
1529 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1636 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1700 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1716 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
DARMISelLowering.cpp304 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
332 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
395 for (unsigned im = (unsigned)ISD::PRE_INC; in addMVEVectorTypes()
1023 for (unsigned im = (unsigned)ISD::PRE_INC; in ARMTargetLowering()
15558 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
102 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal); in PPCTargetLowering()
103 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal); in PPCTargetLowering()
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp813 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
849 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
869 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
948 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1379 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1448 ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm7Offset()
1576 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1683 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
1747 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
1763 isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryMVEIndexedLoad()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp905 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
941 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
961 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
1040 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1368 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1479 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryARMIndexedLoad()
1555 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in tryT2IndexedLoad()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp173 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
174 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
175 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
176 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
177 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
178 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
179 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
180 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
181 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
182 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
[all …]
DPPCISelDAGToDAG.cpp4629 ST->getAddressingMode() != ISD::PRE_INC) in Select()
4640 if (LD->getAddressingMode() != ISD::PRE_INC) { in Select()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp365 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp194 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
195 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
196 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
197 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
198 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
199 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
200 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
201 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
202 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
203 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
[all …]
DPPCISelDAGToDAG.cpp4760 ST->getAddressingMode() != ISD::PRE_INC) in Select()
4771 if (LD->getAddressingMode() != ISD::PRE_INC) { in Select()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td876 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
886 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td1136 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1147 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td1143 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
1154 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp625 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp856 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp735 for (unsigned IM = (unsigned)ISD::PRE_INC; in initActions()

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