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Searched refs:Pseudo (Results 1 – 25 of 343) sorted by relevance

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/external/llvm-project/llvm/test/Analysis/BlockFrequencyInfo/
Ddouble_exit.ll16 ; Pseudo-edges = exit
17 ; Pseudo-mass = 1
29 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
30 ; Pseudo-mass = 2/3
89 ; Pseudo-edges = exit
90 ; Pseudo-mass = 1
102 ; Pseudo-edges = outer.inc
103 ; Pseudo-mass = 1/2
115 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
116 ; Pseudo-mass = 2/3
/external/llvm/test/Analysis/BlockFrequencyInfo/
Ddouble_exit.ll16 ; Pseudo-edges = exit
17 ; Pseudo-mass = 1
29 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
30 ; Pseudo-mass = 2/3
89 ; Pseudo-edges = exit
90 ; Pseudo-mass = 1
102 ; Pseudo-edges = outer.inc
103 ; Pseudo-mass = 1/2
115 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
116 ; Pseudo-mass = 2/3
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td107 Pseudo Pseudo = !cast<Pseudo>(NAME); // Used as a key.
119 let Fields = [ "Pseudo", "BaseInstr", "VLIndex", "SEWIndex", "MergeOpIndex",
121 let PrimaryKey = [ "Pseudo" ];
135 BaseInstr = !cast<Instruction>(!subst("Pseudo", "", NAME)) in
136 def "_"# vlmul.MX : Pseudo<(outs result_reg_class:$rd),
196 // Pseudo instructions and patterns.
207 def PseudoVSETVLI : Pseudo<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei), []>;
231 : Pseudo<(outs vreg:$rd),
247 : Pseudo<(outs),
302 // Pseudo instructions.
DRISCVInstrInfoA.td128 // Pseudo-instructions and codegen patterns
182 /// Pseudo AMOs
184 class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
207 : Pseudo<(outs GPR:$res, GPR:$scratch),
216 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
227 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
236 class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
240 class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
274 : Pseudo<(outs GPR:$res, GPR:$scratch),
284 multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst> {
[all …]
DRISCVInstrFormats.td144 // Pseudo instructions
145 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
152 // Pseudo load instructions.
154 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
163 … : Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
171 // Pseudo store instructions.
173 … : Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
/external/llvm/lib/Target/X86/
DX86InstrCompiler.td30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
94 def VAARG_64 : I<0, Pseudo,
109 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
116 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrInfo.td63 // Pseudo shift nodes for non-constant shift amounts.
343 def ADJCALLSTACKDOWN : Pseudo<(outs),
353 def ADJCALLSTACKUP : Pseudo<(outs),
377 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
382 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
400 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
407 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
446 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
464 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
494 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
/external/llvm/lib/Target/AVR/
DAVRInstrInfo.td64 // Pseudo shift nodes for non-constant shift amounts.
301 def ADJCALLSTACKDOWN : Pseudo<(outs),
311 def ADJCALLSTACKUP : Pseudo<(outs),
335 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
340 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
358 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
365 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
404 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
422 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
452 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
/external/llvm-project/llvm/lib/Target/AVR/
DAVRInstrInfo.td63 // Pseudo shift nodes for non-constant shift amounts.
349 def ADJCALLSTACKDOWN : Pseudo<(outs),
359 def ADJCALLSTACKUP : Pseudo<(outs),
383 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
388 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
406 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
413 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
452 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
470 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
500 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenInstrInfo.inc4861 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
4862 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4863 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
4864 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4865 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4866 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4867 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4868 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4869 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
4870 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]
/external/llvm/include/llvm/CodeGen/
DValueTypes.td102 // Pseudo valuetype mapped to the current pointer size to any address space.
106 // Pseudo valuetype to represent "vector of any size"
109 // Pseudo valuetype to represent "float of any format"
112 // Pseudo valuetype to represent "integer of any bit width"
115 // Pseudo valuetype mapped to the current pointer size.
118 // Pseudo valuetype to represent "any type of any size".
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrTSX.td23 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
34 // Pseudo instruction to fake the definition of EAX on the fallback code path.
36 def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
DX86InstrCompiler.td24 // Random Pseudo Instructions.
31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
43 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
58 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
73 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
87 def VAARG_64 : I<0, Pseudo,
102 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
109 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrTSX.td23 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
34 // Pseudo instruction to fake the definition of EAX on the fallback code path.
36 def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
DX86InstrCompiler.td24 // Random Pseudo Instructions.
31 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
43 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
58 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
61 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
73 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
87 def VAARG_64 : I<0, Pseudo,
102 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
109 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrFormats.td28 // Pseudo instructions
29 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td128 // Pseudo-instructions and codegen patterns
182 /// Pseudo AMOs
184 class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
207 : Pseudo<(outs GPR:$res, GPR:$scratch),
216 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
227 : Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
236 class PseudoMaskedAMOPat<Intrinsic intrin, Pseudo AMOInst>
240 class PseudoMaskedAMOMinMaxPat<Intrinsic intrin, Pseudo AMOInst>
274 : Pseudo<(outs GPR:$res, GPR:$scratch),
284 multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst> {
[all …]
DRISCVInstrFormats.td104 // Pseudo instructions
105 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
112 // Pseudo load instructions.
114 : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
123 … : Pseudo<(outs rdty:$rd, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr, $tmp"> {
131 // Pseudo store instructions.
133 … : Pseudo<(outs rsty:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
/external/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
209 def ATOMIC_LOAD_ADD_I64 : Pseudo<
212 def ATOMIC_LOAD_SUB_I64 : Pseudo<
215 def ATOMIC_LOAD_OR_I64 : Pseudo<
218 def ATOMIC_LOAD_XOR_I64 : Pseudo<
221 def ATOMIC_LOAD_AND_I64 : Pseudo<
224 def ATOMIC_LOAD_NAND_I64 : Pseudo<
228 def ATOMIC_CMP_SWAP_I64 : Pseudo<
232 def ATOMIC_SWAP_I64 : Pseudo<
265 def TCRETURNdi8 :Pseudo< (outs),
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonPseudo.td25 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
203 : Pseudo<(outs), iops, "">, PredRel {
246 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
249 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
425 def PS_vstorerq_ai: Pseudo<(outs),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td25 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
82 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
86 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
203 : Pseudo<(outs), iops, "">, PredRel {
246 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
249 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
425 def PS_vstorerq_ai: Pseudo<(outs),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/VE/
DVEInstrFormats.td70 // Pseudo instructions.
71 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern=[]>
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DValueTypes.td172 // Pseudo valuetype mapped to the current pointer size to any address space.
176 // Pseudo valuetype to represent "vector of any size"
179 // Pseudo valuetype to represent "float of any format"
182 // Pseudo valuetype to represent "integer of any bit width"
185 // Pseudo valuetype mapped to the current pointer size.
188 // Pseudo valuetype to represent "any type of any size".
/external/python/cpython2/Doc/library/
Dpty.rst2 :mod:`pty` --- Pseudo-terminal utilities
7 :synopsis: Pseudo-Terminal Handling for Linux.
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenInstrInfo.inc2984 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
2985 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
2986 …{ 2, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<M…
2987 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2988 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2989 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2990 …{ 6, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
2991 …{ 7, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
2992 …{ 8, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
2993 …{ 9, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
[all …]

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