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Searched refs:QPR (Results 1 – 25 of 32) sorted by relevance

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/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrNEON.td558 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
560 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
564 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
568 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
984 : PseudoNLdSt<(outs QPR:$dst),
985 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
988 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
989 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1035 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1060 def : Pat<(vector_insert (v8f16 QPR:$src),
[all …]
DARMRegisterInfo.td449 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16, v8bf16], 128,
452 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)];
459 // Subset of QPR that have 32-bit SPR subregs.
461 128, (trunc QPR, 8)> {
465 // Subset of QPR that have DPR_8 and SPR_8 subregs.
467 128, (trunc QPR, 4)> {
472 // parsing assembly, since we still have to truncate the register set in the QPR
475 128, (trunc QPR, 8)>;
488 128, (interleave QPR, TuplesOE2D)> {
491 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)),
[all …]
DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
DA15SDOptimizer.cpp69 bool QPR = false);
419 unsigned Lane, bool QPR) { in createDupLane() argument
421 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane()
423 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrNEON.td582 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
584 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
588 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
592 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1008 : PseudoNLdSt<(outs QPR:$dst),
1009 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1012 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1013 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1059 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1084 def : Pat<(vector_insert (v8f16 QPR:$src),
[all …]
DARMRegisterInfo.td438 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
441 let AltOrders = [(rotl QPR, 8), (trunc QPR, 8)];
448 // Subset of QPR that have 32-bit SPR subregs.
450 128, (trunc QPR, 8)> {
454 // Subset of QPR that have DPR_8 and SPR_8 subregs.
456 128, (trunc QPR, 4)> {
461 // parsing assembly, since we still have to truncate the register set in the QPR
464 128, (trunc QPR, 8)>;
477 128, (interleave QPR, TuplesOE2D)> {
480 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16)),
[all …]
DARMRegisterBanks.td13 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
DA15SDOptimizer.cpp69 bool QPR = false);
419 unsigned Lane, bool QPR) { in createDupLane() argument
421 MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : &ARM::DPRRegClass); in createDupLane()
423 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td625 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
627 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
631 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
635 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1026 : PseudoNLdSt<(outs QPR:$dst),
1027 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1030 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
1031 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1076 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1100 def : Pat<(vector_insert (v4f32 QPR:$src),
[all …]
DARMRegisterInfo.td313 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
316 let AltOrders = [(rotl QPR, 8)];
320 // Subset of QPR that have 32-bit SPR subregs.
322 128, (trunc QPR, 8)>;
324 // Subset of QPR that have DPR_8 and SPR_8 subregs.
326 128, (trunc QPR, 4)>;
339 128, (interleave QPR, TuplesOE2D)> {
342 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
371 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
DA15SDOptimizer.cpp72 bool QPR = false);
429 unsigned Lane, bool QPR) { in createDupLane() argument
430 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane()
435 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), in createDupLane()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc1247 …} (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4…
1248 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
1255 …} (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vd), (and:{ *:[v2i64] } QPR:{ *:[v2…
1256 … // Dst: (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vd, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
2017 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, (xor:{ *:…
2018 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2044 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } QPR:{ *:[v4i3…
2045 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
2068 …QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } (xor:{ *:[v4i32] } (bitconvert:{…
2069 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
[all …]
DARMGenInstrInfo.inc14849 QPR = 320,
19527 OpTypes::QPR,
19713 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
19714 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
19715 OpTypes::QPR, OpTypes::QPR,
19716 OpTypes::QPR, OpTypes::QPR,
20737 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
20738 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
20741 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
20742 OpTypes::QPR, OpTypes::QPR, OpTypes::QPR,
[all …]
DARMGenGlobalISel.inc1825 …R:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i6…
1854 …R:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i6…
1883 …QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1662:{ *:[iPTR] }, …
1912 …QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i32] } 1663:{ *:[iPTR] }, …
1981 … } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64…
2001 … } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64…
2021 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VAD…
2041 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VAD…
2057 …// (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } …
2263 …R:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i3…
[all …]
/external/clang/test/CodeGenCXX/
Dnested-base-member-access.cpp15 void QPR() { printf("iQ = %d\n", iQ); } in QPR() function
39 this->MPR(); this->PPR(); this->QPR(); in PR()
Dconstructor-init.cpp25 void QPR() {printf("iQ = %d\n", iQ); }; in QPR() function
40 QPR(); in PR()
/external/llvm-project/clang/test/CodeGenCXX/
Dnested-base-member-access.cpp15 void QPR() { printf("iQ = %d\n", iQ); } in QPR() function
39 this->MPR(); this->PPR(); this->QPR(); in PR()
Dconstructor-init.cpp25 void QPR() {printf("iQ = %d\n", iQ); }; in QPR() function
40 QPR(); in PR()
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc9414 // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)
9425 // (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)
9462 // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)
9473 // (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)
9526 // (VBICiv4i32 QPR:$Vd, nImmSplatNotI32:$imm, pred:$p)
9535 // (VBICiv8i16 QPR:$Vd, nImmSplatNotI16:$imm, pred:$p)
9561 // (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9574 // (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9613 // (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
9626 // (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)
[all …]
DARMGenRegisterInfo.inc1509 // QPR Register Class...
1510 static MCPhysReg QPR[] = {
1514 // QPR Bit set.
2213 { QPR, QPRBits, 1730, 16, sizeof(QPRBits), ARM_QPRRegClassID, 16, 16, 1, 1 },
/external/llvm-project/llvm/test/CodeGen/ARM/
Da15-SD-dep.ll56 ; Test that DPair can be successfully passed as QPR.
Dcoalesce-subregs.ll322 ; once under rare circumstances. When widening a register from QPR to DTriple
/external/llvm/test/CodeGen/ARM/
Da15-SD-dep.ll60 ; Test that DPair can be successfully passed as QPR.
Dcoalesce-subregs.ll322 ; once under rare circumstances. When widening a register from QPR to DTriple
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-phireg.ll4 ; verify-machineinstrs previously caught the incorrect use of QPR in the stack reloads.

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