Searched refs:RCC_PLLNCFGR1_DIVN_MASK (Results 1 – 2 of 2) sorted by relevance
323 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) macro
780 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()1408 RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_check_pll_conf()1543 RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_config()