| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 213 int RCID = Desc.OpInfo[i].RegClass; in encodeInstruction() local
214 const MCRegisterClass &RC = MRI.getRegClass(RCID); in encodeInstruction()
283 int RCID = Desc.OpInfo[OpNo].RegClass; in getMachineOpValue() local
284 const MCRegisterClass &RC = MRI.getRegClass(RCID); in getMachineOpValue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 134 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
135 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
282 const TargetRegisterClass *getRegClass(unsigned RCID) const;
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| D | SIRegisterInfo.cpp | 1830 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
1831 switch ((int)RCID) { in getRegClass()
1840 return AMDGPURegisterInfo::getRegClass(RCID); in getRegClass()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 98 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID()
99 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
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| D | SIInstrInfo.cpp | 1860 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass() local
1861 return RI.getRegClass(RCID); in getOpRegClass()
1881 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove() local
1882 const TargetRegisterClass *RC = RI.getRegClass(RCID); in legalizeOpWithMove()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 154 bool isSGPRClassID(unsigned RCID) const { in isSGPRClassID() argument
155 return isSGPRClass(getRegClass(RCID)); in isSGPRClassID()
287 const TargetRegisterClass *getRegClass(unsigned RCID) const;
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| D | AMDGPUTargetTransformInfo.h | 170 unsigned getNumberOfRegisters(unsigned RCID) const;
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| D | AMDGPUTargetTransformInfo.cpp | 276 unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const { in getNumberOfRegisters()
278 const TargetRegisterClass *RC = TRI->getRegClass(RCID); in getNumberOfRegisters()
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| D | SIRegisterInfo.cpp | 2061 SIRegisterInfo::getRegClass(unsigned RCID) const { in getRegClass()
2062 switch ((int)RCID) { in getRegClass()
2071 return AMDGPUGenRegisterInfo::getRegClass(RCID); in getRegClass()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 900 unsigned RCID; in getRegClassConstraint() local
904 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
905 return TRI->getRegClass(RCID); in getRegClassConstraint()
1747 unsigned RCID = 0; in print() local
1749 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1751 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1753 OS << ":RC" << RCID; in print()
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| D | TargetInstrInfo.cpp | 1401 unsigned RCID = 0; in createMIROperandComment() local
1403 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in createMIROperandComment()
1405 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in createMIROperandComment()
1407 OS << ":RC" << RCID; in createMIROperandComment()
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1203 unsigned RCID; in getRegClassConstraint() local
1204 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
1205 return TRI->getRegClass(RCID); in getRegClassConstraint()
1828 unsigned RCID = 0; in print() local
1829 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1831 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1833 OS << ":RC" << RCID; in print()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 856 unsigned RCID; in getRegClassConstraint() local
860 InlineAsm::hasRegClassConstraint(Flag, RCID)) in getRegClassConstraint()
861 return TRI->getRegClass(RCID); in getRegClassConstraint()
1631 unsigned RCID = 0; in print() local
1633 InlineAsm::hasRegClassConstraint(Flag, RCID)) { in print()
1635 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); in print()
1637 OS << ":RC" << RCID; in print()
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 386 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
387 if (RCID != -1) { in printOperand()
388 const MCRegisterClass &ImmRC = MRI.getRegClass(RCID); in printOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 1083 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
1084 switch (RCID) { in getRegBitWidth()
1139 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
1140 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
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| D | AMDGPUBaseInfo.h | 586 unsigned getRegBitWidth(unsigned RCID);
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| /external/llvm-project/llvm/lib/Target/AMDGPU/Utils/ |
| D | AMDGPUBaseInfo.cpp | 1255 unsigned getRegBitWidth(unsigned RCID) { in getRegBitWidth() argument
1256 switch (RCID) { in getRegBitWidth()
1327 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getRegOperandSize() local
1328 return getRegBitWidth(MRI->getRegClass(RCID)) / 8; in getRegOperandSize()
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| D | AMDGPUBaseInfo.h | 633 unsigned getRegBitWidth(unsigned RCID);
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 246 bool isRegClass(unsigned RCID) const { in isRegClass()
247 return isReg() && Reg.TRI->getRegClass(RCID).contains(getReg()); in isRegClass()
932 int RCID = getRegClass(RegKind, RegWidth); in ParseAMDGPURegister() local
933 if (RCID == -1) in ParseAMDGPURegister()
935 const MCRegisterClass RC = TRI->getRegClass(RCID); in ParseAMDGPURegister()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 246 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
247 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type); in isRegOrImmWithInputMods()
365 bool isRegClass(unsigned RCID) const;
369 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
370 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); in isRegOrInlineNoMods()
1637 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
1638 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2130 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2131 if (RCID == -1) in getRegularReg()
2135 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 277 bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { in isRegOrImmWithInputMods() argument
278 return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type); in isRegOrImmWithInputMods()
401 bool isRegClass(unsigned RCID) const;
405 bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { in isRegOrInlineNoMods() argument
406 return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); in isRegOrInlineNoMods()
1748 bool AMDGPUOperand::isRegClass(unsigned RCID) const { in isRegClass()
1749 return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); in isRegClass()
2286 int RCID = getRegClass(RegKind, RegWidth); in getRegularReg() local
2287 if (RCID == -1) { in getRegularReg()
2293 const MCRegisterClass RC = TRI->getRegClass(RCID); in getRegularReg()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 579 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
580 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUInstPrinter.cpp | 669 int RCID = Desc.OpInfo[OpNo].RegClass; in printOperand() local
670 unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID)); in printOperand()
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| /external/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1467 unsigned RCID; in handleSpecialFP() local
1485 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FloatingPoint.cpp | 1532 unsigned RCID; in handleSpecialFP() local
1550 if (InlineAsm::hasRegClassConstraint(Flags, RCID)) { in handleSpecialFP()
|