Searched refs:REG_DWORD_OFFSET (Results 1 – 5 of 5) sorted by relevance
| /external/google-breakpad/src/third_party/libdisasm/ |
| D | ia32_implicit.c | 43 {{ OP_R | OP_W, REG_DWORD_OFFSET },
56 {{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}}; /* cmpxchg */
60 {{ OP_R | OP_W, REG_DWORD_OFFSET },
61 { OP_R | OP_W, REG_DWORD_OFFSET + 2 },
62 { OP_R, REG_DWORD_OFFSET + 1 },
63 { OP_R, REG_DWORD_OFFSET + 3 }, {0}}; /* cmpxchg8b */
67 {{ OP_R | OP_W, REG_DWORD_OFFSET },
68 { OP_W, REG_DWORD_OFFSET + 1 },
69 { OP_W, REG_DWORD_OFFSET + 2 },
70 { OP_W, REG_DWORD_OFFSET + 3 }, {0}}; /* cpuid */
[all …]
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| D | ia32_reg.c | 38 { REG_DWORD_OFFSET, 0 }, /* al : 1 */
39 { REG_DWORD_OFFSET, 8 }, /* ah : 2 */
40 { REG_DWORD_OFFSET, 0 }, /* ax : 3 */
41 { REG_DWORD_OFFSET + 1, 0 }, /* cl : 4 */
42 { REG_DWORD_OFFSET + 1, 8 }, /* ch : 5 */
43 { REG_DWORD_OFFSET + 1, 0 }, /* cx : 6 */
44 { REG_DWORD_OFFSET + 2, 0 }, /* dl : 7 */
45 { REG_DWORD_OFFSET + 2, 8 }, /* dh : 8 */
46 { REG_DWORD_OFFSET + 2, 0 }, /* dx : 9 */
47 { REG_DWORD_OFFSET + 3, 0 }, /* bl : 10 */
[all …]
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| D | ia32_settings.c | 11 REG_DWORD_OFFSET, REG_SEG_OFFSET, REG_FPU_OFFSET,
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| D | ia32_operand.c | 183 REG_DWORD_OFFSET + 6 ); in decode_operand_value()
190 REG_DWORD_OFFSET + 7 ); in decode_operand_value()
413 gen_regs = REG_DWORD_OFFSET; in ia32_decode_operand()
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| D | ia32_reg.h | 8 #define REG_DWORD_OFFSET 1 /* 0 + 1 */ macro
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