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Searched refs:RSI (Results 1 – 25 of 116) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp89 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
90 return RSI.Instr == Instr; in operator ==()
110 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
112 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
117 void trackRSI(const RegSeqInfo &RSI);
198 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
200 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
201 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
208 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
209 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp81 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
82 return RSI.Instr == Instr; in operator ==()
96 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
98 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
104 void trackRSI(const RegSeqInfo &RSI);
180 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
182 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
183 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
190 for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
191 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp88 bool operator==(const RegSeqInfo &RSI) const { in operator ==()
89 return RSI.Instr == Instr; in operator ==()
109 bool tryMergeUsingCommonSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
111 bool tryMergeUsingFreeSlot(RegSeqInfo &RSI, RegSeqInfo &CompatibleRSI,
116 void trackRSI(const RegSeqInfo &RSI);
202 RegSeqInfo *RSI, const RegSeqInfo *BaseRSI, in RebuildVector() argument
204 Register Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
205 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
212 for (DenseMap<Register, unsigned>::iterator It = RSI->RegToChan.begin(), in RebuildVector()
213 E = RSI->RegToChan.end(); It != E; ++It) { in RebuildVector()
[all …]
/external/llvm/test/CodeGen/X86/
Dor-lea.ll12 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
27 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
42 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
57 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
72 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
89 ; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
/external/llvm-project/llvm/test/tools/llvm-dwarfdump/X86/
Ddebug_loclists.s21 # REGULAR-NEXT: [0x0000000000000004, 0x0000000000000005): DW_OP_reg4 RSI
22 # VERBOSE-NEXT: [0x0000000000000004, 0x0000000000000005) ".text": DW_OP_reg4 RSI
33 # BOTH-NEXT: DW_LLE_startx_length (0x000000000000dead, 0x0000000000000001): DW_OP_reg4 RSI)
45 # REGULAR-NEXT: [0x0000000000000004, 0x0000000000000005): DW_OP_reg4 RSI
47 # VERBOSE-NEXT: => [0x0000000000000004, 0x0000000000000005) ".text": DW_OP_reg4 RSI
63 # BOTH-NEXT: DW_LLE_startx_length (0x000000000000dead, 0x0000000000000001): DW_OP_reg4 RSI
/external/swiftshader/third_party/marl/src/
Dosfiber_asm_x64.h47 uintptr_t RSI; member
70 static_assert(offsetof(marl_fiber_context, RSI) == MARL_REG_RSI,
Dosfiber_x64.c35 ctx->RSI = (uintptr_t)arg; in marl_fiber_set_target()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.h330 RegSizeInfoByHwMode RSI; variable
459 RegSizeInfoByHwMode RSI; member
462 : Members(M), RSI(I) {} in Key()
465 : Members(&RC.getMembers()), RSI(RC.RSI) {} in Key()
DRegisterBankEmitter.cpp88 else if (RCWithLargestRegsSize->RSI.get(DefaultMode).SpillSize < in addRegisterClass()
89 RC->RSI.get(DefaultMode).SpillSize) in addRegisterClass()
250 unsigned Size = RC.RSI.get(DefaultMode).SpillSize; in emitBaseClassImplementation()
DCodeGenRegisters.cpp792 RSI = RegSizeInfoByHwMode(DI->getDef(), RegBank.getHwModes()); in CodeGenRegisterClass()
794 assert((RSI.hasDefault() || Size != 0 || VTs[0].isSimple()) && in CodeGenRegisterClass()
796 if (!RSI.hasDefault()) { in CodeGenRegisterClass()
801 RSI.Map.insert({DefaultMode, RI}); in CodeGenRegisterClass()
819 TopoSigs(RegBank.getNumTopoSigs()), EnumValue(-1), RSI(Props.RSI), in CodeGenRegisterClass()
874 OS << "{ " << K.RSI; in operator <<()
887 return std::tie(*Members, RSI) < std::tie(*B.Members, B.RSI); in operator <()
901 return A->RSI.isSubClassOf(B->RSI) && in testSubClass()
920 if (A->RSI < B->RSI) in TopoOrderRC()
922 if (A->RSI != B->RSI) in TopoOrderRC()
[all …]
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp109 X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RBP, X86::RSP, in initLLVMToSEHAndCVRegMapping()
285 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
313 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
350 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
386 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
422 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
423 return X86::RSI; in getX86SubSuperRegisterOrZero()
/external/strace/linux/x86_64/
Darch_regs.h18 #define RSI 13 macro
Duserent.h14 XLAT(8*RSI),
/external/kernel-headers/original/uapi/asm-x86/asm/
Dptrace-abi.h47 #define RSI 104 macro
/external/llvm/lib/Target/X86/
DX86CallingConv.td233 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
312 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
374 RDI, RSI, RDX, RCX, R8, R9,
463 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
476 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
769 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
863 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
869 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
879 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
888 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
[all …]
/external/llvm-project/llvm/test/tools/llvm-exegesis/X86/
Danalysis-clustering-algorithms.test197 - 'ROL64ri RSI RSI i_0x1'
214 - 'RSI=0x0'
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp160 {codeview::RegisterId::RSI, X86::RSI}, in initLLVMToSEHAndCVRegMapping()
607 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
635 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
672 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
708 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
744 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
745 return X86::RSI; in getX86SubSuperRegisterOrZero()
/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp158 {codeview::RegisterId::RSI, X86::RSI}, in initLLVMToSEHAndCVRegMapping()
619 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
647 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
684 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
720 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
756 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: in getX86SubSuperRegisterOrZero()
757 return X86::RSI; in getX86SubSuperRegisterOrZero()
/external/llvm/utils/TableGen/
DCodeGenSchedule.cpp1042 RSI = PTI->ReadSequences.begin(), RSE = PTI->ReadSequences.end(); in hasVariant() local
1043 RSI != RSE; ++RSI) { in hasVariant()
1045 RI = RSI->begin(), RE = RSI->end(); RI != RE; ++RI) { in hasVariant()
1279 RSI = Trans.ReadSequences.begin(), RSE = Trans.ReadSequences.end(); in substituteVariants() local
1280 RSI != RSE; ++RSI) { in substituteVariants()
1286 substituteVariantOperand(*RSI, /*IsRead=*/true, StartIdx); in substituteVariants()
1308 RSI = I->ReadSequences.begin(), RSE = I->ReadSequences.end(); in inferFromTransitions() local
1309 RSI != RSE; ++RSI) { in inferFromTransitions()
1312 SchedModels.findOrInsertRW(*RSI, /*IsRead=*/true)); in inferFromTransitions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
424 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
523 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
585 RDI, RSI, RDX, RCX, R8, R9,
678 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
699 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
984 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
1077 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1087 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
427 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
529 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
591 RDI, RSI, RDX, RCX, R8, R9,
684 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
705 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
991 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
1084 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1094 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
[all …]
/external/llvm-project/llvm/test/tools/llvm-objdump/COFF/
Dwin64-unwind-data.test22 OBJ-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
71 EXE-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
/external/llvm/test/tools/llvm-objdump/
Dwin64-unwind-data.test22 OBJ-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
71 EXE-NEXT: 0x09: UOP_SaveNonVol RSI [0x0010]
/external/llvm-project/llvm/test/DebugInfo/X86/
Dparameters.ll30 ; CHECK-NEXT: DW_OP_breg4 RSI+0, DW_OP_deref
41 ; CHECK-NEXT: {{.*}}: DW_OP_breg4 RSI+0, DW_OP_deref
/external/llvm-project/llvm/test/DebugInfo/MIR/X86/
Ddbgcall-site-interpretation.mir16 # CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)
17 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg4 RSI))
21 # CHECK-NEXT: DW_AT_GNU_call_site_value (DW_OP_GNU_entry_value(DW_OP_reg4 RSI))
30 # CHECK-NEXT: DW_AT_location (DW_OP_reg4 RSI)

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