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Searched refs:RegClassID (Results 1 – 25 of 25) sorted by relevance

/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp163 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
165 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
186 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
188 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
DAMDGPUDisassembler.h44 const char* getRegClassName(unsigned RegClassID) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.h58 const char* getRegClassName(unsigned RegClassID) const;
61 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
DAMDGPUDisassembler.cpp593 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
595 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
614 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
616 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
618 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/external/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.h59 const char* getRegClassName(unsigned RegClassID) const;
62 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
DAMDGPUDisassembler.cpp635 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
637 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
656 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
658 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
660 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/external/capstone/contrib/sysz_update/
D0001-capstone-generate-GenRegisterInfo.inc.patch87 - OS << " " << RC.getName() << "RegClassID"
88 + OS << " " << NAME_PREFIX RC.getName() << "RegClassID"
280 - << RC.getQualifiedName() + "RegClassID" << ", "
286 + << "RegClassID" << ", "
/external/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp506 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
507 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
510 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); in scavengeRegister()
534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp864 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
918 bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1294 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1296 switch (RegClassID) { in GetSIDIForRegClass()
1330 int RegClassID = -1; in VerifyAndAdjustOperands() local
1351 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1352 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1358 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1360 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1362 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp289 unsigned RegClassID; in Select() local
296 RegClassID = selectSGPRVectorRegClassID(NumVectorElts); in Select()
303 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break; in Select()
306 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID; in Select()
308 RegClassID = AMDGPU::R600_Reg128RegClassID; in Select()
315 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
330 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in Select()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp686 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1026 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1028 switch (RegClassID) { in GetSIDIForRegClass()
1062 int RegClassID = -1; in VerifyAndAdjustOperands() local
1083 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1084 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1090 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1092 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1094 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1101 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp164 void SelectBuildVector(SDNode *N, unsigned RegClassID);
681 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
686 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
701 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
804 unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); in Select() local
805 SelectBuildVector(N, RegClassID); in Select()
2791 unsigned RegClassID; in Select() local
2797 case 2: RegClassID = R600::R600_Reg64RegClassID; break; in Select()
2800 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
2802 RegClassID = R600::R600_Reg128RegClassID; in Select()
[all …]
/external/llvm-project/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp1085 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1143 bool parseSEHRegisterNumber(unsigned RegClassID, unsigned &RegNo);
1611 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1613 switch (RegClassID) { in GetSIDIForRegClass()
1647 int RegClassID = -1; in VerifyAndAdjustOperands() local
1668 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1669 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1675 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1677 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1679 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUISelDAGToDAG.cpp164 void SelectBuildVector(SDNode *N, unsigned RegClassID);
663 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
668 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
685 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
790 unsigned RegClassID = in Select() local
792 SelectBuildVector(N, RegClassID); in Select()
3058 unsigned RegClassID; in Select() local
3064 case 2: RegClassID = R600::R600_Reg64RegClassID; break; in Select()
3067 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
3069 RegClassID = R600::R600_Reg128RegClassID; in Select()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
DAArch64RegisterInfo.td647 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
849 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
901 # RegClassSuffix # "RegClassID>";
940 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1117 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
DAArch64RegisterInfo.td631 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
829 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
880 # RegClassSuffix # "RegClassID>";
919 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1096 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
/external/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1559 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1567 unsigned Register = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo); in DecodeGPRSeqPairsClassRegisterClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1776 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1784 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/external/llvm-project/llvm/lib/Target/AArch64/Disassembler/
DAArch64Disassembler.cpp1812 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1820 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1145 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1147 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1150 template <unsigned RegClassID, int ExtWidth>
1155 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/external/llvm-project/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp1186 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1188 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1191 template <unsigned RegClassID, int ExtWidth>
1196 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1733 template<unsigned Bits, unsigned RegClassID>
1736 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()
/external/llvm-project/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp1799 template<unsigned Bits, unsigned RegClassID>
1802 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) in isMemImm7ShiftedOffset()