| /external/llvm-project/lldb/source/Plugins/Process/Linux/ |
| D | NativeRegisterContextLinux_x86_64.cpp | 714 if (IsCPUFeatureAvailable(RegSet::avx)) { in ReadAllRegisterValues()
729 if (IsCPUFeatureAvailable(RegSet::mpx)) { in ReadAllRegisterValues()
812 if (IsCPUFeatureAvailable(RegSet::avx)) { in WriteAllRegisterValues()
827 if (IsCPUFeatureAvailable(RegSet::mpx)) { in WriteAllRegisterValues()
846 RegSet feature_code) const { in IsCPUFeatureAvailable()
852 case RegSet::gpr: in IsCPUFeatureAvailable()
853 case RegSet::fpu: in IsCPUFeatureAvailable()
855 case RegSet::avx: // Check if CPU has AVX and if there is kernel support, by in IsCPUFeatureAvailable()
860 case RegSet::mpx: // Check if CPU has MPX and if there is kernel support, by in IsCPUFeatureAvailable()
873 switch (static_cast<RegSet>(set_index)) { in IsRegisterSetAvailable()
[all …]
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| D | NativeRegisterContextLinux_x86_64.h | 68 enum class RegSet { gpr, fpu, avx, mpx }; enum
109 bool IsCPUFeatureAvailable(RegSet feature_code) const;
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 69 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
255 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
258 if (RegSet.count(*AI)) in isRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 69 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
255 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
258 if (RegSet.count(*AI)) in isRegInSet()
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiDelaySlotFiller.cpp | 70 bool isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg);
257 bool Filler::isRegInSet(SmallSet<unsigned, 32> &RegSet, unsigned Reg) { in isRegInSet() argument
260 if (RegSet.count(*AI)) in isRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 274 using RegSet = SparseSet<IndexMaskPair>; variable
275 RegSet Regs;
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 257 typedef SparseSet<IndexMaskPair> RegSet;
258 RegSet Regs;
279 RegSet::const_iterator I = Regs.find(SparseIndex);
302 RegSet::iterator I = Regs.find(SparseIndex);
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RegisterPressure.h | 274 using RegSet = SparseSet<IndexMaskPair>; variable
275 RegSet Regs;
297 RegSet::const_iterator I = Regs.find(SparseIndex); in contains()
320 RegSet::iterator I = Regs.find(SparseIndex); in erase()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 75 typedef DenseSet<unsigned> RegSet; typedef
83 RegSet regsLive;
86 RegSet regsLiveInButUnused;
108 RegSet regsKilled;
112 RegSet regsLiveOut;
116 RegSet vregsPassed;
120 RegSet vregsRequired;
138 bool addPassed(const RegSet &RS) { in addPassed()
140 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) in addPassed()
157 bool addRequired(const RegSet &RS) { in addRequired()
[all …]
|
| D | RegAllocPBQP.cpp | 120 typedef std::set<unsigned> RegSet; typedef in __anon6c1893590111::RegAllocPBQP
124 RegSet VRegsToAlloc, EmptyIntervalVRegs;
708 for (RegSet::const_iterator in finalizeAlloc()
|
| /external/capstone/ |
| D | MCRegisterInfo.h | 31 const uint8_t *RegSet; member
|
| D | MCRegisterInfo.c | 142 return (c->RegSet[Byte] & (1 << InByte)) != 0; in MCRegisterClass_contains()
|
| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 78 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
346 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
351 if (RegSet.count(*AI)) in IsRegInSet()
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 75 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
343 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
348 if (RegSet.count(*AI)) in IsRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 75 bool IsRegInSet(SmallSet<unsigned, 32>& RegSet,
343 bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) in IsRegInSet() argument
348 if (RegSet.count(*AI)) in IsRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineVerifier.cpp | 108 using RegSet = DenseSet<unsigned>; typedef
117 RegSet regsLive;
141 RegSet regsKilled;
145 RegSet regsLiveOut;
149 RegSet vregsPassed;
153 RegSet vregsRequired;
171 bool addPassed(const RegSet &RS) { in addPassed()
173 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) in addPassed()
190 bool addRequired(const RegSet &RS) { in addRequired()
192 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) in addRequired()
[all …]
|
| D | RegAllocPBQP.cpp | 150 using RegSet = std::set<unsigned>; typedef in __anonfcc6133b0111::RegAllocPBQP
154 RegSet VRegsToAlloc, EmptyIntervalVRegs;
748 for (RegSet::const_iterator in finalizeAlloc()
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 36 const uint8_t *const RegSet; variable
72 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 115 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
416 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
419 if (RegSet.test(*AI)) in isRegInSet()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 133 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
447 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
450 if (RegSet.test(*AI)) in isRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 133 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const;
448 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { in isRegInSet() argument
451 if (RegSet.test(*AI)) in isRegInSet()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 37 const uint8_t *const RegSet; variable
73 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
|
| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 37 const uint8_t *const RegSet; variable
73 return (RegSet[Byte] & (1 << InByte)) != 0; in contains()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RegAllocPBQP.cpp | 149 using RegSet = std::set<Register>; typedef in __anon3d96ddc70111::RegAllocPBQP
153 RegSet VRegsToAlloc, EmptyIntervalVRegs;
762 for (RegSet::const_iterator in finalizeAlloc()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonExpandCondsets.cpp | 245 void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
556 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet, in updateLiveness() argument
559 for (auto R : RegSet) { in updateLiveness()
|