| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 424 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping() local
426 if (RegTy.isScalar() && in getInstrMapping()
427 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64)) in getInstrMapping()
430 if (RegTy.isVector() && RegTy.getSizeInBits() != 128) in getInstrMapping()
|
| D | MipsISelLowering.cpp | 4340 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
4341 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4349 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
4368 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
4380 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
4407 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
4419 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
4423 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
4459 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
4460 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 453 LLT RegTy = MRI.getType(Op.getReg()); in getInstrMapping() local
455 if (RegTy.isScalar() && in getInstrMapping()
456 (RegTy.getSizeInBits() != 32 && RegTy.getSizeInBits() != 64)) in getInstrMapping()
459 if (RegTy.isVector() && RegTy.getSizeInBits() != 128) in getInstrMapping()
|
| D | MipsISelLowering.cpp | 4354 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
4355 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
4363 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
4383 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
4395 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
4422 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
4434 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
4438 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
4473 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
4474 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); in repairReg() local
177 if (RegTy.isVector()) { in repairReg()
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements()) in repairReg()
183 RegTy.getSizeInBits()) && in repairReg()
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() == in repairReg()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegBankSelect.cpp | 174 LLT RegTy = MRI->getType(MO.getReg()); in repairReg() local
177 if (RegTy.isVector()) { in repairReg()
178 if (ValMapping.NumBreakDowns == RegTy.getNumElements()) in repairReg()
183 RegTy.getSizeInBits()) && in repairReg()
184 (ValMapping.BreakDown[0].Length % RegTy.getScalarSizeInBits() == in repairReg()
|
| D | Utils.cpp | 503 LLT RegTy) { in getFunctionLiveInPhysReg() argument
522 if (RegTy.isValid()) in getFunctionLiveInPhysReg()
523 MRI.setType(LiveIn, RegTy); in getFunctionLiveInPhysReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 95 const LLT RegTy = getType(Reg); in constrainRegAttrs() local
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() && in constrainRegAttrs()
98 RegTy != ConstrainingRegTy) in constrainRegAttrs()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 95 const LLT RegTy = getType(Reg); in constrainRegAttrs() local
97 if (RegTy.isValid() && ConstrainingRegTy.isValid() && in constrainRegAttrs()
98 RegTy != ConstrainingRegTy) in constrainRegAttrs()
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 1487 const LLT RegTy = MRI.getType(DstReg); in selectDivRem() local
1488 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectDivRem()
1563 [RegTy](const DivRemEntry &El) { in selectDivRem()
1564 return El.SizeInBits == RegTy.getSizeInBits(); in selectDivRem()
1590 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); in selectDivRem()
1616 if (RegTy.getSizeInBits() == 16) { in selectDivRem()
1620 } else if (RegTy.getSizeInBits() == 32) { in selectDivRem()
1624 } else if (RegTy.getSizeInBits() == 64) { in selectDivRem()
|
| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64CallLowering.cpp | 92 const LLT RegTy = MRI.getType(ValVReg); in assignValueToAddress() local
93 MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize); in assignValueToAddress()
197 const LLT RegTy = MRI.getType(ValVReg); in assignValueToAddress() local
198 if (RegTy.getSizeInBytes() > Size) in assignValueToAddress()
199 Size = RegTy.getSizeInBytes(); in assignValueToAddress()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 1531 const LLT RegTy = MRI.getType(DstReg); in selectDivRem() local
1532 assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) && in selectDivRem()
1607 [RegTy](const DivRemEntry &El) { in selectDivRem()
1608 return El.SizeInBits == RegTy.getSizeInBits(); in selectDivRem()
1634 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB); in selectDivRem()
1660 if (RegTy.getSizeInBits() == 16) { in selectDivRem()
1664 } else if (RegTy.getSizeInBits() == 32) { in selectDivRem()
1668 } else if (RegTy.getSizeInBits() == 64) { in selectDivRem()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 213 LLT RegTy = LLT());
|
| D | LegalizerHelper.h | 183 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 150 const LLT RegTy = MRI.getType(ValVReg); in assignValueToAddress() local
151 MemSize = std::min(static_cast<uint64_t>(RegTy.getSizeInBytes()), MemSize); in assignValueToAddress()
258 const LLT RegTy = MRI.getType(ValVReg); in assignValueToAddress() local
259 if (RegTy.getSizeInBytes() > Size) in assignValueToAddress()
260 Size = RegTy.getSizeInBytes(); in assignValueToAddress()
|
| D | AMDGPULegalizerInfo.cpp | 4284 LLT RegTy; in legalizeImageIntrinsic() local
4289 RegTy = S32; in legalizeImageIntrinsic()
4296 RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32; in legalizeImageIntrinsic()
4350 ResultRegs[I] = MRI->createGenericVirtualRegister(RegTy); in legalizeImageIntrinsic()
4380 if (RegTy != V2S16 && !ST.hasUnpackedD16VMem()) { in legalizeImageIntrinsic()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizerHelper.h | 148 bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4767 class VDOT<bit op6, bit op4, bit op23, RegisterClass RegTy, string Asm,
4770 N3Vnp<{0b1100, op23}, 0b10, 0b1101, op6, op4, (outs RegTy:$dst),
4771 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4773 [(set (AccumTy RegTy:$dst),
4774 (OpNode (AccumTy RegTy:$Vd),
4775 (InputTy RegTy:$Vn),
4776 (InputTy RegTy:$Vm)))]> {
4834 multiclass N3VMixedDotLane<bit Q, bit U, string Asm, string AsmTy, RegisterClass RegTy,
4838 def "" : N3Vnp<0b11101, 0b00, 0b1101, Q, U, (outs RegTy:$dst),
4839 (ins RegTy:$Vd, RegTy:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), N3RegFrm,
[all …]
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3752 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); in copyByValRegs() local
3753 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
3761 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), in copyByValRegs()
3781 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in passByValArg() local
3793 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, in passByValArg()
3821 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), in passByValArg()
3834 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal, in passByValArg()
3838 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift); in passByValArg()
3874 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); in writeVarArgRegs() local
3875 const TargetRegisterClass *RC = getRegClassFor(RegTy); in writeVarArgRegs()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 204 struct RegTy { struct
218 struct RegTy Reg;
|
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 183 struct RegTy { struct
197 struct RegTy Reg;
|
| /external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 206 struct RegTy { struct
220 struct RegTy Reg;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1494 template <VecListIndexType RegTy, unsigned NumRegs>
1509 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) && in addVectorListOperands()
1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands()
1514 FirstRegs[(unsigned)RegTy][0])); in addVectorListOperands()
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1535 template <VecListIndexType RegTy, unsigned NumRegs>
1550 assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) && in addVectorListOperands()
1553 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands()
1555 FirstRegs[(unsigned)RegTy][0])); in addVectorListOperands()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4836 class VDOT<bit op6, bit op4, RegisterClass RegTy, string Asm, string AsmTy,
4839 N3Vnp<0b11000, 0b10, 0b1101, op6, op4, (outs RegTy:$dst),
4840 (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm), N3RegFrm, IIC_VDOTPROD,
4842 [(set (AccumTy RegTy:$dst),
4843 (OpNode (AccumTy RegTy:$Vd),
4844 (InputTy RegTy:$Vn),
4845 (InputTy RegTy:$Vm)))]> {
|