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Searched refs:SIGN_EXTEND_VECTOR_INREG (Results 1 – 25 of 38) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h435 SIGN_EXTEND_VECTOR_INREG, enumerator
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DISDOpcodes.h569 SIGN_EXTEND_VECTOR_INREG, enumerator
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h718 SIGN_EXTEND_VECTOR_INREG, enumerator
/external/llvm-project/llvm/unittests/CodeGen/
DAArch64SelectionDAGTest.cpp145 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
159 auto Op = DAG->getNode(ISD::SIGN_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec); in TEST_F()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp329 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
683 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
DSelectionDAGDumper.cpp246 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
DLegalizeVectorTypes.cpp622 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
2130 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
2441 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2458 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
DLegalizeIntegerTypes.cpp106 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3357 case ISD::SIGN_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp67 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
394 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
860 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
1979 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2786 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
3253 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3362 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3378 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4317 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
DSelectionDAGDumper.cpp324 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
DLegalizeVectorOps.cpp440 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
854 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
DTargetLowering.cpp1711 case ISD::SIGN_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1716 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
2513 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp68 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
404 case ISD::SIGN_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
919 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorResult()
2112 case ISD::SIGN_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2944 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVectorResult()
3420 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, WidenVT, InOp); in WidenVecRes_Convert()
3525 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
3541 case ISD::SIGN_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
4484 return DAG.getNode(ISD::SIGN_EXTEND_VECTOR_INREG, DL, VT, InOp); in WidenVecOp_EXTEND()
DLegalizeVectorOps.cpp437 case ISD::SIGN_EXTEND_VECTOR_INREG: in LegalizeOp()
735 case ISD::SIGN_EXTEND_VECTOR_INREG: in Expand()
DSelectionDAGDumper.cpp334 case ISD::SIGN_EXTEND_VECTOR_INREG: return "sign_extend_vector_inreg"; in getOperationName()
DTargetLowering.cpp789 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyMultipleUseDemandedBits()
1887 case ISD::SIGN_EXTEND_VECTOR_INREG: { in SimplifyDemandedBits()
1892 bool IsVecInReg = Op.getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG; in SimplifyDemandedBits()
2747 case ISD::SIGN_EXTEND_VECTOR_INREG: in SimplifyDemandedVectorElts()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp84 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
139 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp100 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
163 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DTargetLoweringBase.cpp698 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp899 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp816 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86ISelLowering.cpp1017 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
1018 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
1019 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
1102 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1307 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1543 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1800 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v32i16, Custom); in X86TargetLowering()
2016 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG); in X86TargetLowering()
6011 case ISD::SIGN_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6012 return ISD::SIGN_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86ISelLowering.cpp1024 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v2i64, Custom); in X86TargetLowering()
1025 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v4i32, Custom); in X86TargetLowering()
1026 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, MVT::v8i16, Custom); in X86TargetLowering()
1117 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1335 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
1590 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in X86TargetLowering()
2004 setTargetDAGCombine(ISD::SIGN_EXTEND_VECTOR_INREG); in X86TargetLowering()
6270 case ISD::SIGN_EXTEND_VECTOR_INREG: in getOpcode_EXTEND()
6286 case ISD::SIGN_EXTEND_VECTOR_INREG: in getOpcode_EXTEND_VECTOR_INREG()
6287 return ISD::SIGN_EXTEND_VECTOR_INREG; in getOpcode_EXTEND_VECTOR_INREG()
[all …]
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4577 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
4778 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp373 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
5197 case ISD::SIGN_EXTEND_VECTOR_INREG: in LowerOperation()
5510 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG || in combineExtract()

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