| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | bitwise.mir | 317 ; MIPS32: [[SLLV:%[0-9]+]]:gpr32 = SLLV [[COPY]], [[COPY1]]
318 ; MIPS32: $v0 = COPY [[SLLV]]
|
| /external/llvm-project/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 124 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips2/ |
| D | valid.s | 160 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips3/ |
| D | valid.s | 226 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 222 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1321 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1324 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1584 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1589 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1593 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
|
| D | MipsFastISel.cpp | 1765 Opcode = Mips::SLLV; in selectShift()
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_32.c | 403 EMIT_SHIFT(SLL, SLLV); in emit_single_op()
|
| D | sljitNativeMIPS_64.c | 499 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV); in emit_single_op()
|
| /external/llvm-project/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 270 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 270 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 271 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1797 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1800 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1984 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1989 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1993 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
|
| D | MipsScheduleP5600.td | 225 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
|
| D | MipsInstrInfo.td | 2083 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
2835 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
2841 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
| D | MipsFastISel.cpp | 2022 Opcode = Mips::SLLV; in selectShift()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1795 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicBinaryPartword()
1798 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt); in emitAtomicBinaryPartword()
1982 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask) in emitAtomicCmpSwapPartword()
1987 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal) in emitAtomicCmpSwapPartword()
1991 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal) in emitAtomicCmpSwapPartword()
|
| D | MipsScheduleP5600.td | 226 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
|
| D | MipsInstrInfo.td | 2084 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
2880 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
2886 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
|
| /external/llvm-project/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 287 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 286 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 305 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 366 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 359 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|
| /external/llvm-project/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 353 # CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
|