| /external/llvm/unittests/Support/ |
| D | ScaledNumberTest.cpp | 40 typedef ScaledPair<uint64_t> SP64; typedef
49 EXPECT_EQ(getRounded64(0, 0, false), SP64(0, 0)); in TEST()
50 EXPECT_EQ(getRounded64(0, 0, true), SP64(1, 0)); in TEST()
51 EXPECT_EQ(getRounded64(20, 21, true), SP64(21, 21)); in TEST()
52 EXPECT_EQ(getRounded64(UINT32_MAX, 0, false), SP64(UINT32_MAX, 0)); in TEST()
53 EXPECT_EQ(getRounded64(UINT32_MAX, 0, true), SP64(UINT64_C(1) << 32, 0)); in TEST()
54 EXPECT_EQ(getRounded64(UINT64_MAX, 0, false), SP64(UINT64_MAX, 0)); in TEST()
55 EXPECT_EQ(getRounded64(UINT64_MAX, 0, true), SP64(UINT64_C(1) << 63, 1)); in TEST()
70 EXPECT_EQ(getAdjusted64(0), SP64(0, 0)); in TEST()
71 EXPECT_EQ(getAdjusted64(0, 5), SP64(0, 5)); in TEST()
[all …]
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| /external/llvm-project/llvm/unittests/Support/ |
| D | ScaledNumberTest.cpp | 39 typedef ScaledPair<uint64_t> SP64; typedef
48 EXPECT_EQ(getRounded64(0, 0, false), SP64(0, 0)); in TEST()
49 EXPECT_EQ(getRounded64(0, 0, true), SP64(1, 0)); in TEST()
50 EXPECT_EQ(getRounded64(20, 21, true), SP64(21, 21)); in TEST()
51 EXPECT_EQ(getRounded64(UINT32_MAX, 0, false), SP64(UINT32_MAX, 0)); in TEST()
52 EXPECT_EQ(getRounded64(UINT32_MAX, 0, true), SP64(UINT64_C(1) << 32, 0)); in TEST()
53 EXPECT_EQ(getRounded64(UINT64_MAX, 0, false), SP64(UINT64_MAX, 0)); in TEST()
54 EXPECT_EQ(getRounded64(UINT64_MAX, 0, true), SP64(UINT64_C(1) << 63, 1)); in TEST()
69 EXPECT_EQ(getAdjusted64(0), SP64(0, 0)); in TEST()
70 EXPECT_EQ(getAdjusted64(0, 5), SP64(0, 5)); in TEST()
[all …]
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrCall.td | 19 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in {
24 } // Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1
27 let Uses = [SP32, SP64], isCall = 1 in {
78 } // Uses = [SP32,SP64], isCall = 1
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| D | WebAssemblyRegisterInfo.td | 33 def SP64 : WebAssemblyReg<"%SP64">;
64 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
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| D | WebAssemblyRegisterInfo.cpp | 47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs()
146 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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| D | WebAssemblyFrameLowering.cpp | 128 ? WebAssembly::SP64 in getSPReg()
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| D | WebAssemblyISelLowering.cpp | 54 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrCall.td | 21 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in {
36 let Uses = [SP32, SP64], isCall = 1 in {
48 } // Uses = [SP32,SP64], isCall = 1
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| D | WebAssemblyRegisterInfo.td | 34 def SP64 : WebAssemblyReg<"%SP64">;
56 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64)>;
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| D | WebAssemblyRegisterInfo.cpp | 48 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs()
129 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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| D | WebAssemblyISelLowering.cpp | 51 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyInstrCall.td | 19 let Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1 in {
24 } // Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1
57 let Uses = [SP32, SP64], isCall = 1 in {
119 } // Uses = [SP32,SP64], isCall = 1
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| D | WebAssemblyRegisterInfo.td | 33 def SP64 : WebAssemblyReg<"%SP64">;
62 def I64 : WebAssemblyRegClass<[i64], 64, (add FP64, SP64, I64_0)>;
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| D | WebAssemblyRegisterInfo.cpp | 47 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32, in getReservedRegs()
137 /* !hasFP */ {WebAssembly::SP32, WebAssembly::SP64}, in getFrameRegister()
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| D | WebAssemblyISelLowering.cpp | 53 Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32); in WebAssemblyTargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 2545 // SP64 Register Class...
2546 const MCPhysReg SP64[] = {
2550 // SP64 Bit set.
2737 { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 1, false },
4020 { 64, 64, 64, VTLists+2 }, // SP64
7045 { // SP64
7046 64, // sub_32 -> SP64
7212 {1, 1}, // SP64
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| D | MipsGenAsmMatcher.inc | 1967 MCK_SP64, // register class 'SP64'
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| D | MipsGenInstrInfo.inc | 10828 SP64 = 221,
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| /external/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 459 def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 491 def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 491 def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;
|