| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 947 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
954 assert(SrcOps.size() == 3 && "Invalid select"); in buildInstr()
956 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
957 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); in buildInstr()
976 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
978 SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
979 SrcOps[1].getLLTTy(*getMRI())); in buildInstr()
986 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
988 SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
989 SrcOps[1].getLLTTy(*getMRI())); in buildInstr()
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| D | CSEMIRBuilder.cpp | 91 ArrayRef<SrcOp> SrcOps, in profileEverything() argument
99 profileSrcOps(SrcOps, B); in profileEverything()
139 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
158 assert(SrcOps.size() == 2 && "Invalid sources"); in buildInstr()
160 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), in buildInstr()
161 SrcOps[1].getReg(), *getMRI())) in buildInstr()
167 assert(SrcOps.size() == 2 && "Invalid src ops"); in buildInstr()
169 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
170 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
179 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
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| D | LegalizerHelper.cpp | 2380 SmallVector<SrcOp, 4> SrcOps; in fewerElementsVectorBasic() local
2384 SrcOps.push_back(PartOpReg); in fewerElementsVectorBasic()
2388 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags); in fewerElementsVectorBasic()
2396 SmallVector<SrcOp, 4> SrcOps; in fewerElementsVectorBasic() local
2401 SrcOps.push_back(PartOpReg); in fewerElementsVectorBasic()
2405 MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags); in fewerElementsVectorBasic()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 976 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
983 assert(SrcOps.size() == 3 && "Invalid select"); in buildInstr()
985 DstOps[0].getLLTTy(*getMRI()), SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
986 SrcOps[1].getLLTTy(*getMRI()), SrcOps[2].getLLTTy(*getMRI())); in buildInstr()
993 assert(SrcOps.size() == 1 && "Invalid Srcs"); in buildInstr()
995 SrcOps[0].getLLTTy(*getMRI())); in buildInstr()
1017 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
1019 SrcOps[0].getLLTTy(*getMRI()), in buildInstr()
1020 SrcOps[1].getLLTTy(*getMRI())); in buildInstr()
1029 assert(SrcOps.size() == 2 && "Invalid Srcs"); in buildInstr()
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| D | CSEMIRBuilder.cpp | 106 ArrayRef<SrcOp> SrcOps, in profileEverything() argument
114 profileSrcOps(SrcOps, B); in profileEverything()
169 ArrayRef<SrcOp> SrcOps, in buildInstr() argument
188 assert(SrcOps.size() == 2 && "Invalid sources"); in buildInstr()
190 if (Optional<APInt> Cst = ConstantFoldBinOp(Opc, SrcOps[0].getReg(), in buildInstr()
191 SrcOps[1].getReg(), *getMRI())) in buildInstr()
197 assert(SrcOps.size() == 2 && "Invalid src ops"); in buildInstr()
199 const SrcOp &Src0 = SrcOps[0]; in buildInstr()
200 const SrcOp &Src1 = SrcOps[1]; in buildInstr()
209 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 29 ArrayRef<SrcOp> SrcOps,
48 assert(SrcOps.size() == 2 && "Invalid src ops");
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
59 assert(SrcOps.size() == 2 && "Invalid src ops");
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
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| D | CSEMIRBuilder.h | 73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
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| D | MachineIRBuilder.h | 1481 ArrayRef<SrcOp> SrcOps,
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 29 ArrayRef<SrcOp> SrcOps,
48 assert(SrcOps.size() == 2 && "Invalid src ops");
50 const SrcOp &Src0 = SrcOps[0];
51 const SrcOp &Src1 = SrcOps[1];
59 assert(SrcOps.size() == 2 && "Invalid src ops");
61 const SrcOp &Src0 = SrcOps[0];
62 const SrcOp &Src1 = SrcOps[1];
69 return MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps);
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| D | CSEMIRBuilder.h | 73 ArrayRef<SrcOp> SrcOps, Optional<unsigned> Flags,
95 ArrayRef<SrcOp> SrcOps,
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| D | MachineIRBuilder.h | 1796 ArrayRef<SrcOp> SrcOps,
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64PostLegalizerLowering.cpp | 51 SmallVector<SrcOp, 2> SrcOps; ///< Source registers. member
53 std::initializer_list<SrcOp> SrcOps) in ShuffleVectorPseudo()
54 : Opc(Opc), Dst(Dst), SrcOps(SrcOps){}; in ShuffleVectorPseudo()
362 MIRBuilder.buildInstr(MatchInfo.Opc, {MatchInfo.Dst}, MatchInfo.SrcOps); in applyShuffleVectorPseudo()
374 MIRBuilder.buildConstant(LLT::scalar(32), MatchInfo.SrcOps[2].getImm()); in applyEXT()
376 {MatchInfo.SrcOps[0], MatchInfo.SrcOps[1], Cst}); in applyEXT()
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| D | AArch64InstructionSelector.cpp | 185 std::initializer_list<llvm::SrcOp> SrcOps,
4009 std::initializer_list<llvm::SrcOp> SrcOps, MachineIRBuilder &MIRBuilder, in emitInstr() argument
4014 auto MI = MIRBuilder.buildInstr(Opcode, DstOps, SrcOps); in emitInstr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 20573 SmallVectorImpl<SDValue> &SrcOps) { in matchScalarReduction() argument
20616 SrcOps.push_back(Src); in matchScalarReduction()
34082 ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root, in combineX86ShufflesRecursively() argument
34097 SDValue Op = SrcOps[SrcOpIndex]; in combineX86ShufflesRecursively()
34151 Ops.append(SrcOps.begin(), SrcOps.end()); in combineX86ShufflesRecursively()
40294 SmallVector<SDValue, 2> SrcOps; in combineAnd() local
40295 if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps) && in combineAnd()
40296 SrcOps.size() == 1) { in combineAnd()
40299 unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements(); in combineAnd()
40301 SDValue Mask = combineBitcastvxi1(DAG, MaskVT, SrcOps[0], dl, Subtarget); in combineAnd()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 21718 SmallVectorImpl<SDValue> &SrcOps, in matchScalarReduction() argument
21762 SrcOps.push_back(Src); in matchScalarReduction()
21774 for (SDValue &SrcOp : SrcOps) in matchScalarReduction()
36097 ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root, in combineX86ShufflesRecursively() argument
36114 SDValue Op = SrcOps[SrcOpIndex]; in combineX86ShufflesRecursively()
36178 Ops.append(SrcOps.begin(), SrcOps.end()); in combineX86ShufflesRecursively()
43579 SmallVector<SDValue, 2> SrcOps; in combineAnd() local
43581 if (matchScalarReduction(SDValue(N, 0), ISD::AND, SrcOps, &SrcPartials) && in combineAnd()
43582 SrcOps.size() == 1) { in combineAnd()
43585 unsigned NumElts = SrcOps[0].getValueType().getVectorNumElements(); in combineAnd()
[all …]
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 19400 SmallVector<SDValue, 4> SrcOps; in combineConcatVectorOfCasts() local
19405 SrcOps.push_back(Op.getOperand(0)); in combineConcatVectorOfCasts()
19435 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatSrcVT, SrcOps); in combineConcatVectorOfCasts()
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