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Searched refs:SubIdx (Results 1 – 25 of 153) sorted by relevance

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/external/llvm/lib/CodeGen/
DDetectDeadLanes.cpp245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
246 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
251 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
260 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
270 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
320 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
321 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
[all …]
DTargetRegisterInfo.cpp46 unsigned SubIdx) { in PrintReg() argument
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) { in PrintReg()
58 if (SubIdx) { in PrintReg()
60 OS << ':' << TRI->getSubRegIndexName(SubIdx); in PrintReg()
62 OS << ":sub(" << SubIdx << ')'; in PrintReg()
DExpandPostRAPseudos.cpp90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/llvm-project/llvm/lib/CodeGen/
DDetectDeadLanes.cpp239 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
240 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
243 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
245 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
254 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
263 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
264 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
313 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
314 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
315 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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DExpandPostRAPseudos.cpp86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
88 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DDetectDeadLanes.cpp242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
243 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
246 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
248 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
257 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx); in transferUsedLanes()
266 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
267 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes); in transferUsedLanes()
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
317 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes); in transferDefinedLanes()
318 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx); in transferDefinedLanes()
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DExpandPostRAPseudos.cpp86 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
88 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
89 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
DTargetRegisterInfo.cpp90 unsigned SubIdx, const MachineRegisterInfo *MRI) { in printReg() argument
91 return Printable([Reg, TRI, SubIdx, MRI](raw_ostream &OS) { in printReg()
111 if (SubIdx) { in printReg()
113 OS << ':' << TRI->getSubRegIndexName(SubIdx); in printReg()
115 OS << ":sub(" << SubIdx << ')'; in printReg()
/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
371 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
373 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
381 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
382 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
501 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
DTargetInstrInfo.h171 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
250 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
281 unsigned SubIdx, const MachineInstr &Orig,
367 unsigned SubIdx; member
369 unsigned SubIdx = 0)
370 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h338 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
339 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
341 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
348 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
349 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
350 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
516 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
518 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1148 unsigned SubIdx = 0,
/external/llvm-project/llvm/utils/TableGen/
DCodeGenRegisters.cpp134 CodeGenSubRegIndex *SubIdx = *I; in computeConcatTransitiveClosure() local
135 SubIdx->computeConcatTransitiveClosure(); in computeConcatTransitiveClosure()
137 for (CodeGenSubRegIndex *SRI : SubIdx->ConcatenationOf) in computeConcatTransitiveClosure()
141 if (SubIdx->ConcatenationOf.empty()) { in computeConcatTransitiveClosure()
145 I = ConcatenationOf.insert(I, SubIdx->ConcatenationOf.begin(), in computeConcatTransitiveClosure()
146 SubIdx->ConcatenationOf.end()); in computeConcatTransitiveClosure()
147 I += SubIdx->ConcatenationOf.size(); in computeConcatTransitiveClosure()
502 for (CodeGenSubRegIndex *SubIdx : SubRegIdx->ConcatenationOf) in computeSecondarySubRegs()
503 Parts.push_back(SubIdx); in computeSecondarySubRegs()
537 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
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DCodeGenRegisters.h384 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
385 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
398 const CodeGenSubRegIndex *SubIdx) const;
400 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
402 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
407 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
411 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
413 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
/external/llvm-project/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h344 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
345 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
347 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
354 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
355 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
356 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
535 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg() argument
537 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
1202 unsigned SubIdx = 0,
/external/llvm/utils/TableGen/
DCodeGenRegisters.h349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
DCodeGenRegisters.cpp469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
900 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1566 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1567 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1570 if (SuperIdx == SubIdx) in pruneUnitSets()
1579 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
/external/llvm-project/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstructionSelector.cpp205 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
207 SubIdx = X86::sub_32bit; in getSubRegIndex()
209 SubIdx = X86::sub_16bit; in getSubRegIndex()
211 SubIdx = X86::sub_8bit; in getSubRegIndex()
214 return SubIdx; in getSubRegIndex()
743 unsigned SubIdx; in selectTruncOrPtrToInt() local
746 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
748 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
750 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
752 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
460 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
502 SubIdx == DefSubIdx && in EmitSubregNode()
517 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
527 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
551 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
572 MIB.addImm(SubIdx); in EmitSubregNode()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstructionSelector.cpp204 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
206 SubIdx = X86::sub_32bit; in getSubRegIndex()
208 SubIdx = X86::sub_16bit; in getSubRegIndex()
210 SubIdx = X86::sub_8bit; in getSubRegIndex()
213 return SubIdx; in getSubRegIndex()
742 unsigned SubIdx; in selectTruncOrPtrToInt() local
745 SubIdx = X86::NoSubRegister; in selectTruncOrPtrToInt()
747 SubIdx = X86::sub_32bit; in selectTruncOrPtrToInt()
749 SubIdx = X86::sub_16bit; in selectTruncOrPtrToInt()
751 SubIdx = X86::sub_8bit; in selectTruncOrPtrToInt()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
465 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx); in ConstrainForSubReg()
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
516 SubIdx == DefSubIdx && in EmitSubregNode()
532 Reg = ConstrainForSubReg(Reg, SubIdx, in EmitSubregNode()
544 CopyMI.addReg(Reg, 0, SubIdx); in EmitSubregNode()
546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx)); in EmitSubregNode()
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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/external/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
/external/llvm/lib/MC/
DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
/external/capstone/
DMCRegisterInfo.c86 unsigned MCRegisterInfo_getMatchingSuperReg(const MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx… in MCRegisterInfo_getMatchingSuperReg() argument
99 if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) in MCRegisterInfo_getMatchingSuperReg()

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