Searched refs:TGSI_OPCODE_I64SHR (Results 1 – 8 of 8) sorted by relevance
| /external/virglrenderer/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 275 { 1, 2, 0, 0, 0, 0, COMP, "I64SHR", TGSI_OPCODE_I64SHR },
468 case TGSI_OPCODE_I64SHR: in tgsi_opcode_infer_type()
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_info.c | 234 case TGSI_OPCODE_I64SHR: in tgsi_opcode_infer_type()
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| D | tgsi_exec.c | 6230 case TGSI_OPCODE_I64SHR: in exec_instruction()
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| /external/mesa3d/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 611 TGSI_OPCODE_I64SHR = 242, enumerator
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| /external/virglrenderer/src/gallium/include/pipe/ |
| D | p_shader_tokens.h | 580 #define TGSI_OPCODE_I64SHR 232 macro
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_from_tgsi.cpp | 625 case TGSI_OPCODE_I64SHR: in inferSrcType()
4023 case TGSI_OPCODE_I64SHR: in handleInstruction()
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| /external/mesa3d/src/gallium/auxiliary/nir/ |
| D | nir_to_tgsi.c | 645 [nir_op_ishr] = { TGSI_OPCODE_ISHR, TGSI_OPCODE_I64SHR }, in ntt_emit_alu()
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| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_tgsi_action.c | 2636 bld_base->op_actions[TGSI_OPCODE_I64SHR].emit = i64shr_emit_cpu; in lp_set_default_actions_cpu()
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