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Searched refs:USHLSAT (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dcombine-shift-of-shifted-logic-shlsat.mir17 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
19 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
45 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
47 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
74 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
76 ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[USHLSAT]], [[USHLSAT1]]
103 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
105 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
131 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C2]](s32)
133 ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[USHLSAT]], [[USHLSAT1]]
[all …]
Dcombine-shift-imm-chain-shlsat.mir126 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C]](s32)
127 ; CHECK: $vgpr0 = COPY [[USHLSAT]](s32)
148 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C]](s32)
149 ; CHECK: $sgpr0 = COPY [[USHLSAT]](s32)
176 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[C1]](s32)
177 ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s32) = G_USHLSAT [[USHLSAT]], [[C]](s32)
204 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[C1]](s64)
205 ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s64) = G_USHLSAT [[USHLSAT]], [[C]](s64)
Dirtranslator-sat.ll329 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s16) = G_USHLSAT [[TRUNC]], [[TRUNC1]](s16)
330 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[USHLSAT]](s16)
346 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s32) = G_USHLSAT [[COPY]], [[COPY1]](s32)
347 ; CHECK: $vgpr0 = COPY [[USHLSAT]](s32)
366 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s64) = G_USHLSAT [[MV]], [[MV1]](s64)
367 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](s64)
388 …; CHECK: [[USHLSAT:%[0-9]+]]:_(<2 x s32>) = G_USHLSAT [[BUILD_VECTOR]], [[BUILD_VECTOR1]](<2 x s…
389 ; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[USHLSAT]](<2 x s32>)
Dcombine-shift-imm-chain-illegal-types.mir293 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s44) = G_USHLSAT [[TRUNC]], [[C]](s44)
294 ; CHECK: [[USHLSAT1:%[0-9]+]]:_(s44) = G_USHLSAT [[USHLSAT]], [[C]](s44)
332 ; CHECK: [[USHLSAT:%[0-9]+]]:_(s55) = G_USHLSAT [[TRUNC]], [[C]](s55)
333 ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[USHLSAT]](s55)
/external/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h340 USHLSAT, enumerator
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp316 case ISD::USHLSAT: return "ushlsat"; in getOperationName()
DLegalizeVectorOps.cpp457 case ISD::USHLSAT: in LegalizeOp()
DLegalizeIntegerTypes.cpp163 case ISD::USHLSAT: Res = PromoteIntRes_ADDSUBSHLSAT(N); break; in PromoteIntegerResult()
738 bool IsShift = Opcode == ISD::USHLSAT || Opcode == ISD::SSHLSAT; in PromoteIntRes_ADDSUBSHLSAT()
766 case ISD::USHLSAT: in PromoteIntRes_ADDSUBSHLSAT()
2144 case ISD::USHLSAT: ExpandIntRes_SHLSAT(N, Lo, Hi); break; in ExpandIntegerResult()
DLegalizeVectorTypes.cpp133 case ISD::USHLSAT: in ScalarizeVectorResult()
1001 case ISD::USHLSAT: in SplitVectorResult()
2892 case ISD::USHLSAT: in WidenVectorResult()
DLegalizeDAG.cpp1139 case ISD::USHLSAT: { in LegalizeOp()
3550 case ISD::USHLSAT: in ExpandNode()
DTargetLowering.cpp7631 Node->getOpcode() == ISD::USHLSAT) && in expandShlSat()
DSelectionDAGBuilder.cpp6281 setValue(&I, DAG.getNode(ISD::USHLSAT, sdl, Op1.getValueType(), Op1, Op2)); in visitIntrinsicCall()
/external/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp768 setOperationAction(ISD::USHLSAT, VT, Expand); in initActions()
/external/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td402 def ushlsat : SDNode<"ISD::USHLSAT" , SDTIntBinOp>;