| /external/llvm/test/CodeGen/AArch64/ |
| D | neon-or-combine.ll | 6 ; (or (and B, A), (and C, ~A)) => (VBSL A, B, C)
|
| /external/llvm-project/llvm/test/CodeGen/AArch64/ |
| D | neon-or-combine.ll | 6 ; (or (and B, A), (and C, ~A)) => (VBSL A, B, C)
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon-nofp16.txt | 1477 VBSL/VBSLQ output:
1478 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1479 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1480 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1481 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1482 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1483 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1484 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1485 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1486 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | ref-rvct-neon.txt | 1569 VBSL/VBSLQ output:
1570 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1571 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1572 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1573 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1574 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1575 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1576 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1577 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1578 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | ref-rvct-all.txt | 1569 VBSL/VBSLQ output:
1570 VBSL/VBSLQ:0:result_int8x8 [] = { fffffff2, fffffff2, fffffff2, fffffff2, fffffff6, fffffff6, fffff…
1571 VBSL/VBSLQ:1:result_int16x4 [] = { fffffff0, fffffff0, fffffff2, fffffff2, }
1572 VBSL/VBSLQ:2:result_int32x2 [] = { fffffff0, fffffff0, }
1573 VBSL/VBSLQ:3:result_int64x1 [] = { fffffffffffffffd, }
1574 VBSL/VBSLQ:4:result_uint8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
1575 VBSL/VBSLQ:5:result_uint16x4 [] = { fff0, fff0, fff2, fff2, }
1576 VBSL/VBSLQ:6:result_uint32x2 [] = { fffffff0, fffffff0, }
1577 VBSL/VBSLQ:7:result_uint64x1 [] = { fffffff1, }
1578 VBSL/VBSLQ:8:result_poly8x8 [] = { f3, f3, f3, f3, f7, f7, f7, f7, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 1384 VBSL/VBSLQ output:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 186 VBSL, enumerator
|
| D | ARMScheduleSwift.td | 546 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
|
| D | ARMInstrNEON.td | 555 def NEONvbsl : SDNode<"ARMISD::VBSL",
5009 // VBSL : Vector Bitwise Select
5085 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
5099 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
8110 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
|
| D | ARMScheduleA9.td | 2402 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMISelLowering.cpp | 1225 case ARMISD::VBSL: return "ARMISD::VBSL"; in getTargetNodeName()
9333 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 246 VBSL, enumerator
|
| D | ARMScheduleR52.td | 790 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)d"…
791 def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL)q…
|
| D | ARMScheduleSwift.td | 562 "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
|
| D | ARMScheduleA57.td | 1204 def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL")>;
|
| D | ARMScheduleA9.td | 2425 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMInstrNEON.td | 517 def NEONvbsl : SDNode<"ARMISD::VBSL",
5440 // VBSL : Vector Bitwise Select
5506 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
5520 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
8846 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
|
| D | ARMISelLowering.cpp | 1678 case ARMISD::VBSL: return "ARMISD::VBSL"; in getTargetNodeName()
12556 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, in PerformORCombine()
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 790 def : InstRW<[R52WriteFPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL|VB…
791 def : InstRW<[R52Write2FPALU_F3, R52Read_F1, R52Read_F2, R52Read_F2], (instregex "(VBIF|VBIT|VBSL|V…
|
| D | ARMScheduleSwift.td | 562 "VBSL", "VBSP", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
|
| D | ARMScheduleA57.td | 1197 def : InstRW<[A57Write_3cyc_1V], (instregex "VBIF", "VBIT", "VBSL", "VBSP")>;
|
| D | ARMScheduleA9.td | 2425 // VADD/VAND/VORR/VEOR/VBIC/VORN/VBIT/VBIF/VBSL
|
| D | ARMInstrNEON.td | 5434 // VBIT/VBIF/VBSL taking into account register constraints to avoid copies.
5496 // VBSL : Vector Bitwise Select
5510 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
5523 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
8965 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 808 def VBSL : SInst<"vbsl", "dudd",
|
| /external/llvm-project/clang/include/clang/Basic/ |
| D | arm_neon.td | 664 def VBSL : SInst<"vbsl", ".U..",
|