| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 933 VECREDUCE_FMAX, VECREDUCE_FMIN, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 73 ; CHECK: [[VECREDUCE_FMAX:%[0-9]+]]:_(s32) = G_VECREDUCE_FMAX [[COPY]](<4 x s32>)
74 ; CHECK: $s0 = COPY [[VECREDUCE_FMAX]](s32)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1145 VECREDUCE_FMAX, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 486 case ISD::VECREDUCE_FMAX: in LegalizeOp()
882 case ISD::VECREDUCE_FMAX: in Expand()
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| D | SelectionDAGDumper.cpp | 470 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 140 case ISD::VECREDUCE_FMAX: in SoftenFloatResult()
2261 case ISD::VECREDUCE_FMAX: in PromoteFloatResult()
2624 case ISD::VECREDUCE_FMAX: in SoftPromoteHalfResult()
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| D | LegalizeVectorTypes.cpp | 627 case ISD::VECREDUCE_FMAX: in ScalarizeVectorOperand()
2128 case ISD::VECREDUCE_FMAX: in SplitVectorOperand()
4400 case ISD::VECREDUCE_FMAX: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1175 case ISD::VECREDUCE_FMAX: in LegalizeOp()
3948 case ISD::VECREDUCE_FMAX: in ExpandNode()
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| D | SelectionDAG.cpp | 373 case ISD::VECREDUCE_FMAX: in getVecReduceBaseOpcode()
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| D | SelectionDAGBuilder.cpp | 9079 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1, SDFlags); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1747 case ISD::VECREDUCE_FMAX: in visit()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 449 case ISD::VECREDUCE_FMAX: return "vecreduce_fmax"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 485 case ISD::VECREDUCE_FMAX: in LegalizeOp()
989 case ISD::VECREDUCE_FMAX: in Expand()
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| D | LegalizeVectorTypes.cpp | 615 case ISD::VECREDUCE_FMAX: in ScalarizeVectorOperand()
1995 case ISD::VECREDUCE_FMAX: in SplitVectorOperand()
2081 case ISD::VECREDUCE_FMAX: in SplitVecOp_VECREDUCE()
4236 case ISD::VECREDUCE_FMAX: in WidenVectorOperand()
4717 case ISD::VECREDUCE_FMAX: in WidenVecOp_VECREDUCE()
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| D | LegalizeDAG.cpp | 1159 case ISD::VECREDUCE_FMAX: in LegalizeOp()
3808 case ISD::VECREDUCE_FMAX: in ExpandNode()
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| D | TargetLowering.cpp | 7622 case ISD::VECREDUCE_FMAX: in expandVecReduce()
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| D | SelectionDAGBuilder.cpp | 9008 Res = DAG.getNode(ISD::VECREDUCE_FMAX, dl, VT, Op1); in visitVectorReduce()
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| D | DAGCombiner.cpp | 1624 case ISD::VECREDUCE_FMAX: in visit()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 723 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 841 setOperationAction(ISD::VECREDUCE_FMAX, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 995 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
1366 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addTypeForFixedLengthSVE()
4291 case ISD::VECREDUCE_FMAX: in LowerOperation()
10237 case ISD::VECREDUCE_FMAX: in LowerVECREDUCE()
10259 case ISD::VECREDUCE_FMAX: { in LowerVECREDUCE()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 359 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in addMVEVectorTypes()
382 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v4f16, Custom); in addMVEVectorTypes()
386 setOperationAction(ISD::VECREDUCE_FMAX, MVT::v2f16, Custom); in addMVEVectorTypes()
9537 case ISD::VECREDUCE_FMAX: BaseOpcode = ISD::FMAXNUM; break; in LowerVecReduce()
9807 case ISD::VECREDUCE_FMAX: in LowerOperation()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 797 setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); in AArch64TargetLowering()
3273 case ISD::VECREDUCE_FMAX: in LowerOperation()
8557 case ISD::VECREDUCE_FMAX: { in LowerVECREDUCE()
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