| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 939 VECREDUCE_SMAX, VECREDUCE_SMIN, VECREDUCE_UMAX, VECREDUCE_UMIN, enumerator
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| /external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ |
| D | irtranslator-reductions.ll | 196 ; CHECK: [[VECREDUCE_SMIN:%[0-9]+]]:_(s32) = G_VECREDUCE_SMIN [[COPY]](<4 x s32>)
197 ; CHECK: $w0 = COPY [[VECREDUCE_SMIN]](s32)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1156 VECREDUCE_SMIN, enumerator
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 481 case ISD::VECREDUCE_SMIN: in LegalizeOp()
877 case ISD::VECREDUCE_SMIN: in Expand()
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| D | SelectionDAGDumper.cpp | 467 case ISD::VECREDUCE_SMIN: return "vecreduce_smin"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 205 case ISD::VECREDUCE_SMIN: in PromoteIntegerResult()
1523 case ISD::VECREDUCE_SMIN: in PromoteIntegerOperand()
1971 case ISD::VECREDUCE_SMIN: in PromoteIntOp_VECREDUCE()
2162 case ISD::VECREDUCE_SMIN: in ExpandIntegerResult()
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| D | LegalizeVectorTypes.cpp | 624 case ISD::VECREDUCE_SMIN: in ScalarizeVectorOperand()
2125 case ISD::VECREDUCE_SMIN: in SplitVectorOperand()
4397 case ISD::VECREDUCE_SMIN: in WidenVectorOperand()
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| D | LegalizeDAG.cpp | 1172 case ISD::VECREDUCE_SMIN: in LegalizeOp()
3945 case ISD::VECREDUCE_SMIN: in ExpandNode()
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| D | SelectionDAG.cpp | 367 case ISD::VECREDUCE_SMIN: in getVecReduceBaseOpcode()
4742 case ISD::VECREDUCE_SMIN: in getNode()
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| D | SelectionDAGBuilder.cpp | 9070 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); in visitVectorReduce()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 446 case ISD::VECREDUCE_SMIN: return "vecreduce_smin"; in getOperationName()
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| D | LegalizeVectorOps.cpp | 480 case ISD::VECREDUCE_SMIN: in LegalizeOp()
984 case ISD::VECREDUCE_SMIN: in Expand()
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| D | LegalizeVectorTypes.cpp | 612 case ISD::VECREDUCE_SMIN: in ScalarizeVectorOperand()
1992 case ISD::VECREDUCE_SMIN: in SplitVectorOperand()
2078 case ISD::VECREDUCE_SMIN: CombineOpc = ISD::SMIN; break; in SplitVecOp_VECREDUCE()
4233 case ISD::VECREDUCE_SMIN: in WidenVectorOperand()
4707 case ISD::VECREDUCE_SMIN: in WidenVecOp_VECREDUCE()
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| D | LegalizeIntegerTypes.cpp | 196 case ISD::VECREDUCE_SMIN: in PromoteIntegerResult()
1319 case ISD::VECREDUCE_SMIN: in PromoteIntegerOperand()
1744 case ISD::VECREDUCE_SMIN: in PromoteIntOp_VECREDUCE()
1925 case ISD::VECREDUCE_SMIN: in ExpandIntegerResult()
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| D | LegalizeDAG.cpp | 1156 case ISD::VECREDUCE_SMIN: in LegalizeOp()
3805 case ISD::VECREDUCE_SMIN: in ExpandNode()
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| D | TargetLowering.cpp | 7619 case ISD::VECREDUCE_SMIN: BaseOpcode = ISD::SMIN; break; in expandVecReduce()
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| D | SelectionDAGBuilder.cpp | 8999 Res = DAG.getNode(ISD::VECREDUCE_SMIN, dl, VT, Op1); in visitVectorReduce()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 720 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 838 setOperationAction(ISD::VECREDUCE_SMIN, VT, Expand); in initActions()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1002 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1093 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
1208 setOperationAction(ISD::VECREDUCE_SMIN, MVT::v2i64, Custom); in AArch64TargetLowering()
1370 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in addTypeForFixedLengthSVE()
4287 case ISD::VECREDUCE_SMIN: in LowerOperation()
10227 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
10253 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
15839 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 430 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 437 def vecreduce_smin : SDNode<"ISD::VECREDUCE_SMIN", SDTVecReduce>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 785 setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); in AArch64TargetLowering()
3270 case ISD::VECREDUCE_SMIN: in LowerOperation()
8551 case ISD::VECREDUCE_SMIN: in LowerVECREDUCE()
12934 case ISD::VECREDUCE_SMIN: in ReplaceNodeResults()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 299 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); in addMVEVectorTypes()
12156 } else if ((TrueVal->getOpcode() == ISD::VECREDUCE_SMIN || in PerformSELECTCombine()
12157 FalseVal->getOpcode() == ISD::VECREDUCE_SMIN) && in PerformSELECTCombine()
12180 case ISD::VECREDUCE_SMIN: in PerformSELECTCombine()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 293 setOperationAction(ISD::VECREDUCE_SMIN, VT, Legal); in addMVEVectorTypes()
|