| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 193 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, enumerator
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| D | ARMInstrNEON.td | 1452 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1453 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1462 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1464 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1466 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1472 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1474 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1476 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
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| D | ARMISelLowering.cpp | 1227 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; in getTargetNodeName()
9961 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; in CombineBaseUpdate()
10128 NewOpc = ARMISD::VLD2DUP; in CombineVLDDUP()
11064 case ARMISD::VLD2DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3148 case ARMISD::VLD2DUP: { in Select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 259 VLD2DUP, enumerator
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| D | ARMInstrNEON.td | 1465 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1466 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1475 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1477 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1479 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1485 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1487 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1489 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
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| D | ARMISelLowering.cpp | 1681 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; in getTargetNodeName()
13152 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; in CombineBaseUpdate()
13316 NewOpc = ARMISD::VLD2DUP; in CombineVLDDUP()
14661 case ARMISD::VLD2DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 3759 case ARMISD::VLD2DUP: { in Select()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 302 VLD2DUP, enumerator
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| D | ARMInstrNEON.td | 1447 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1448 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1457 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1459 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1461 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1467 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1469 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1471 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
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| D | ARMISelLowering.cpp | 1780 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; in getTargetNodeName()
14115 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; in CombineBaseUpdate()
14401 NewOpc = ARMISD::VLD2DUP; in CombineVLDDUP()
16342 case ARMISD::VLD2DUP: in PerformDAGCombine()
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| D | ARMISelDAGToDAG.cpp | 4018 case ARMISD::VLD2DUP: { in Select()
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