Searched refs:VOP1 (Results 1 – 25 of 43) sorted by relevance
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125 Most *VOP1*, *VOP2* and *VOPC* instructions have several variants:134 Native 32-bit encoding (*VOP1*, *VOP2* or *VOPC*) _e32
28 field bit VOP1 = 0;148 let TSFlags{7} = VOP1;213 let hasExtraSrcRegAllocReq = !or(VOP1, VOP2, VOP3, VOPC, SDWA, VALU);
10 // VOP1 Classes55 let VOP1 = 1;149 // VOP1 Instructions177 let VOP1 = 1;834 let VOP1 = 1;
1429 !if (!eq(Src1.Value, untyped.Value), 1, // VOP11449 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst1586 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP11599 // VOP1 without input operands (V_NOP, V_CLREXCP)1604 // VOP1 with modifiers1608 // VOP1 without modifiers1739 // VOP1 without input operands (V_NOP)1783 // VOP1 without input operands (V_NOP)1815 // VOP1 without input operands (V_NOP)1818 // VOP1[all …]
32 VOP1 = 1 << 7, enumerator
412 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()416 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
101 VOP1, VOP2, VOP3, VOPC Instructions107 VOP1, VOP2, and VOPC instructions based on the operands. If you want to force
28 field bit VOP1 = 0;140 let TSFlags{7} = VOP1;207 …let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0)…
10 // VOP1 Classes51 let VOP1 = 1;142 // VOP1 Instructions170 let VOP1 = 1;811 let VOP1 = 1;821 let VOP1 = 1;
1439 !if (!eq(Src1.Value, untyped.Value), 1, // VOP11459 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst1594 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP11607 // VOP1 without input operands (V_NOP, V_CLREXCP)1612 // VOP1 with modifiers1616 // VOP1 without modifiers1747 // VOP1 without input operands (V_NOP)1791 // VOP1 without input operands (V_NOP)1823 // VOP1 without input operands (V_NOP)1826 // VOP1[all …]
406 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()410 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
53 VOP1 = 1 << 8 variable in Format725 VOP1 = { variable821 for (gfx6, gfx7, gfx8, gfx9, gfx10, name, in_mod, out_mod) in VOP1:822 opcode(name, gfx7, gfx9, gfx10, Format.VOP1, in_mod, out_mod)
112 if ((uint32_t)base_format & (uint32_t)Format::VOP1) in validate_ir()113 base_format = Format::VOP1; in validate_ir()136 base_format == Format::VOP1 || in validate_ir()145 base_format == Format::VOP1 || in validate_ir()240 instr->format == Format::VOP1 || in validate_ir()
99 VOP1 = 1 << 8, enumerator242 assert(format == Format::VOP1 || format == Format::VOP2 || format == Format::VOPC); in asSDWA()918 return ((uint16_t) format & (uint16_t) Format::VOP1) == (uint16_t) Format::VOP1 in isVALU()
268 case Format::VOP1: { in emit_instruction()554 } else if ((uint16_t) instr->format & (uint16_t) Format::VOP1) { in emit_instruction()
85 ## VOP1 instructions encoded as VOP3
246 …if (instr->format != Format::VOP1 && instr->format != Format::SOP1 && instr->format != Format::PSE… in should_rematerialize()273 …assert((instr->format == Format::VOP1 || instr->format == Format::SOP1 || instr->format == Format:… in do_reload()278 if (instr->format == Format::VOP1) { in do_reload()
31 field bits<1> VOP1 = 0;67 let TSFlags{10} = VOP1;135 let VOP1 = 1;642 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
28 VOP1 = 1 << 10, enumerator
248 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()252 return get(Opcode).TSFlags & SIInstrFlags::VOP1; in isVOP1()
17 // VOP1 Instructions
29 // VOP1 Instructions
1140 !if (!eq(Src1.Value, untyped.Value), 1, // VOP11190 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP11202 // VOP1 without input operands (V_NOP, V_CLREXCP)1207 // VOP1 with modifiers1211 // VOP1 without modifiers1241 // VOP1 without input operands (V_NOP)1274 // VOP1 without input operands (V_NOP)1700 VOP1<op.SI, outs, ins, asm, []>,1708 VOP1<op.VI, outs, ins, asm, []>,
13 # VOP1:40 ; VOP190 # VOP1:124 ; VOP1533 # Test instruction which does not have modifiers in VOP1 form but does in DPP form.