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Searched refs:ZReg (Results 1 – 16 of 16) sorted by relevance

/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp1110 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; in emitSelect() local
1118 True = ZReg; in emitSelect()
1119 False = ZReg; in emitSelect()
1126 True = ZReg; in emitSelect()
1127 False = ZReg; in emitSelect()
1138 False = ZReg; in emitSelect()
1147 False = ZReg; in emitSelect()
1158 False = ZReg; in emitSelect()
1165 False = ZReg; in emitSelect()
2726 Register ZReg = AArch64::WZR; in select() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3881 static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) { in isMatchingOrAlias() argument
3882 assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31)); in isMatchingOrAlias()
3883 return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) || in isMatchingOrAlias()
3884 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) || in isMatchingOrAlias()
3885 (ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) || in isMatchingOrAlias()
3886 (ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) || in isMatchingOrAlias()
3887 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) || in isMatchingOrAlias()
3888 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0)); in isMatchingOrAlias()
/external/llvm-project/llvm/lib/Target/AArch64/AsmParser/
DAArch64AsmParser.cpp3996 static inline bool isMatchingOrAlias(unsigned ZReg, unsigned Reg) { in isMatchingOrAlias() argument
3997 assert((ZReg >= AArch64::Z0) && (ZReg <= AArch64::Z31)); in isMatchingOrAlias()
3998 return (ZReg == ((Reg - AArch64::B0) + AArch64::Z0)) || in isMatchingOrAlias()
3999 (ZReg == ((Reg - AArch64::H0) + AArch64::Z0)) || in isMatchingOrAlias()
4000 (ZReg == ((Reg - AArch64::S0) + AArch64::Z0)) || in isMatchingOrAlias()
4001 (ZReg == ((Reg - AArch64::D0) + AArch64::Z0)) || in isMatchingOrAlias()
4002 (ZReg == ((Reg - AArch64::Q0) + AArch64::Z0)) || in isMatchingOrAlias()
4003 (ZReg == ((Reg - AArch64::Z0) + AArch64::Z0)); in isMatchingOrAlias()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp3275 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; in emitCMN() local
3277 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()}); in emitCMN()
3299 Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR; in emitTST() local
3307 auto TstMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS}); in emitTST()
3333 Register ZReg; in emitIntegerCompare() local
3340 ZReg = AArch64::WZR; in emitIntegerCompare()
3343 ZReg = AArch64::XZR; in emitIntegerCompare()
3353 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg()); in emitIntegerCompare()
DAArch64FastISel.cpp560 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in fastMaterializeFloatZero() local
562 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
4048 unsigned Opc, ZReg; in emitMul_rr() local
4055 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
4057 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
4063 /*IsKill=*/ZReg, true); in emitMul_rr()
DAArch64InstrInfo.cpp462 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
463 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
480 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
481 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp332 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
333 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
349 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
350 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
DAArch64FastISel.cpp486 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in fastMaterializeFloatZero() local
488 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
3870 unsigned Opc, ZReg; in emitMul_rr() local
3877 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
3879 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
3885 /*IsKill=*/ZReg, true); in emitMul_rr()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagon.td28 "Hexagon ZReg extension instructions">;
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagon.td31 "Hexagon ZReg extension instructions">;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp558 unsigned ZReg = Is64Bit ? AArch64::XZR : AArch64::WZR; in fastMaterializeFloatZero() local
560 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
4041 unsigned Opc, ZReg; in emitMul_rr() local
4048 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
4050 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
4056 /*IsKill=*/ZReg, true); in emitMul_rr()
DAArch64InstrInfo.cpp572 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
573 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
590 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); in canFoldIntoCSel() local
591 if (ZReg != AArch64::XZR && ZReg != AArch64::WZR) in canFoldIntoCSel()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp4142 unsigned ZReg = in expandPostRAPseudo() local
4144 MIB->getOperand(0).setReg(ZReg); in expandPostRAPseudo()
DX86ISelLowering.cpp31496 Register ZReg = MRI.createVirtualRegister(PtrRC); in emitSetJmpShadowStackFix() local
31499 .addDef(ZReg) in emitSetJmpShadowStackFix()
31500 .addReg(ZReg, RegState::Undef) in emitSetJmpShadowStackFix()
31501 .addReg(ZReg, RegState::Undef); in emitSetJmpShadowStackFix()
31506 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitSetJmpShadowStackFix()
31746 Register ZReg = MRI.createVirtualRegister(PtrRC); in emitLongJmpShadowStackFix() local
31749 .addDef(ZReg) in emitLongJmpShadowStackFix()
31750 .addReg(ZReg, RegState::Undef) in emitLongJmpShadowStackFix()
31751 .addReg(ZReg, RegState::Undef); in emitLongJmpShadowStackFix()
31756 BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitLongJmpShadowStackFix()
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrInfo.cpp4689 unsigned ZReg = in expandPostRAPseudo() local
4691 MIB->getOperand(0).setReg(ZReg); in expandPostRAPseudo()
DX86ISelLowering.cpp32805 Register ZReg = MRI.createVirtualRegister(PtrRC); in emitSetJmpShadowStackFix() local
32808 .addDef(ZReg) in emitSetJmpShadowStackFix()
32809 .addReg(ZReg, RegState::Undef) in emitSetJmpShadowStackFix()
32810 .addReg(ZReg, RegState::Undef); in emitSetJmpShadowStackFix()
32815 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitSetJmpShadowStackFix()
33055 Register ZReg = MRI.createVirtualRegister(&X86::GR32RegClass); in emitLongJmpShadowStackFix() local
33056 BuildMI(checkSspMBB, DL, TII->get(X86::MOV32r0), ZReg); in emitLongJmpShadowStackFix()
33062 .addReg(ZReg) in emitLongJmpShadowStackFix()
33064 ZReg = TmpZReg; in emitLongJmpShadowStackFix()
33070 BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg); in emitLongJmpShadowStackFix()