| /external/llvm/unittests/IR/ |
| D | VerifierTest.cpp | 43 Constant *Zero32 = ConstantInt::get(IntegerType::get(C, 32), 0); in TEST() local
44 BI->setOperand(0, Zero32); in TEST()
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| /external/llvm-project/llvm/unittests/IR/ |
| D | VerifierTest.cpp | 42 Constant *Zero32 = ConstantInt::get(IntegerType::get(C, 32), 0); in TEST() local
43 BI->setOperand(0, Zero32); in TEST()
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZTDC.cpp | 360 Value *Zero32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in runOnFunction() local
378 Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32); in runOnFunction()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZTDC.cpp | 346 Value *Zero32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in runOnFunction() local
364 Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32); in runOnFunction()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZTDC.cpp | 346 Value *Zero32 = ConstantInt::get(Type::getInt32Ty(Ctx), 0); in runOnFunction() local
364 Value *ICmp = IRB.CreateICmp(CmpInst::ICMP_NE, TDC, Zero32); in runOnFunction()
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 1609 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass); in selectDivRem() local
1611 Zero32); in selectDivRem()
1619 .addReg(Zero32, 0, X86::sub_16bit); in selectDivRem()
1623 .addReg(Zero32); in selectDivRem()
1628 .addReg(Zero32) in selectDivRem()
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| D | X86FastISel.cpp | 1968 Register Zero32 = createResultReg(&X86::GR32RegClass); in X86SelectDivRem() local
1970 TII.get(X86::MOV32r0), Zero32); in X86SelectDivRem()
1978 .addReg(Zero32, 0, X86::sub_16bit); in X86SelectDivRem()
1982 .addReg(Zero32); in X86SelectDivRem()
1986 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); in X86SelectDivRem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstructionSelector.cpp | 1653 Register Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass); in selectDivRem() local
1655 Zero32); in selectDivRem()
1663 .addReg(Zero32, 0, X86::sub_16bit); in selectDivRem()
1667 .addReg(Zero32); in selectDivRem()
1672 .addReg(Zero32) in selectDivRem()
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| D | X86FastISel.cpp | 1952 unsigned Zero32 = createResultReg(&X86::GR32RegClass); in X86SelectDivRem() local
1954 TII.get(X86::MOV32r0), Zero32); in X86SelectDivRem()
1962 .addReg(Zero32, 0, X86::sub_16bit); in X86SelectDivRem()
1966 .addReg(Zero32); in X86SelectDivRem()
1970 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); in X86SelectDivRem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
| D | GCOVProfiling.cpp | 987 Constant *Zero32 = Builder.getInt32(0); in insertCounterWriteout() local
989 Constant *TwoZero32s[] = {Zero32, Zero32}; in insertCounterWriteout()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1976 const auto Zero32 = B.buildConstant(S32, 0); in legalizeIntrinsicTrunc() local
1979 auto SignBit64 = B.buildMerge(S64, {Zero32, SignBit}); in legalizeIntrinsicTrunc()
1986 auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32); in legalizeIntrinsicTrunc()
2902 auto Zero32 = B.buildConstant(S32, 0); in legalizeUDIV_UREM64Impl() local
2906 auto Add2_Hi = B.buildUAdde(S32, S1, Add2_HiC, Zero32, Add2_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
2943 auto Sub2_Hi = B.buildUSube(S32, S1, Sub2_Mi, Zero32, Sub2_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
2961 auto Sub3_Hi = B.buildUSube(S32, S1, Sub3_Mi, Zero32, Sub3_Lo.getReg(1)); in legalizeUDIV_UREM64Impl()
2969 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Add4, Add3); in legalizeUDIV_UREM64Impl()
2971 B.buildICmp(CmpInst::ICMP_NE, S1, C3, Zero32), Sel1, MulHi3); in legalizeUDIV_UREM64Impl()
2974 S64, B.buildICmp(CmpInst::ICMP_NE, S1, C6, Zero32), Sub3, Sub2); in legalizeUDIV_UREM64Impl()
[all …]
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| /external/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| D | GCOVProfiling.cpp | 1157 Constant *Zero32 = Builder.getInt32(0); in insertCounterWriteout() local
1159 Constant *TwoZero32s[] = {Zero32, Zero32}; in insertCounterWriteout()
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| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1873 unsigned Zero32 = createResultReg(&X86::GR32RegClass); in X86SelectDivRem() local
1875 TII.get(X86::MOV32r0), Zero32); in X86SelectDivRem()
1883 .addReg(Zero32, 0, X86::sub_16bit); in X86SelectDivRem()
1887 .addReg(Zero32); in X86SelectDivRem()
1891 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); in X86SelectDivRem()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1456 const auto Zero32 = B.buildConstant(S32, 0); in legalizeIntrinsicTrunc() local
1459 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)}); in legalizeIntrinsicTrunc()
1466 auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32); in legalizeIntrinsicTrunc()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3858 auto Zero32 = MIRBuilder.buildConstant(S32, 0); in lowerU64ToF32BitOps() local
3867 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); in lowerU64ToF32BitOps()
3887 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); in lowerU64ToF32BitOps()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 5015 auto Zero32 = MIRBuilder.buildConstant(S32, 0); in lowerU64ToF32BitOps() local
5024 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); in lowerU64ToF32BitOps()
5044 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); in lowerU64ToF32BitOps()
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