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Searched refs:add_a (Results 1 – 23 of 23) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_validate_shaders.c116 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in raddr_add_a_to_live_reg_index() local
120 if (add_a == QPU_MUX_A) in raddr_add_a_to_live_reg_index()
122 else if (add_a == QPU_MUX_B && sig != QPU_SIG_SMALL_IMM) in raddr_add_a_to_live_reg_index()
124 else if (add_a <= QPU_MUX_R3) in raddr_add_a_to_live_reg_index()
125 return 64 + add_a; in raddr_add_a_to_live_reg_index()
476 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in track_live_clamps() local
519 (add_a != QPU_MUX_B && add_b != QPU_MUX_B)) { in track_live_clamps()
/external/flatbuffers/tests/evolution_test/
Devolution_v1_generated.h145 void add_a(float a) {
169 builder_.add_a(a);
190 void add_a(int32_t a) {
209 builder_.add_a(a);
295 void add_a(int32_t a) {
356 builder_.add_a(a);
Devolution_v2_generated.h166 void add_a(float a) {
195 builder_.add_a(a);
229 void add_a(int32_t a) {
248 builder_.add_a(a);
275 void add_a(double a) {
298 builder_.add_a(a);
/external/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s59 add_a.b $w26,$w26,$w26
60 add_a.b $w27,$w27,$w27
/external/llvm-project/llvm/test/MC/Mips/
Dmips-reginfo-fp64.s59 add_a.b $w26,$w26,$w26
60 add_a.b $w27,$w27,$w27
/external/flatbuffers/tests/include_test/sub/
Dinclude_test2_generated.rs173 if let Some(x) = args.a { builder.add_a(x); } in create()
202 pub fn add_a(&mut self, a: flatbuffers::WIPOffset<super::super::TableA<'b >>) { in add_a() method
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu.c407 uint32_t add_a = QPU_GET_FIELD(*inst, QPU_ADD_A); in convert_mov() local
413 (add_a != QPU_GET_FIELD(*inst, QPU_ADD_B))) { in convert_mov()
427 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_A); in convert_mov()
428 *inst = QPU_UPDATE_FIELD(*inst, add_a, QPU_MUL_B); in convert_mov()
Dvc4_qpu_schedule.c332 uint32_t add_a = QPU_GET_FIELD(inst, QPU_ADD_A); in calculate_deps() local
346 process_mux_deps(state, n, add_a); in calculate_deps()
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs2 0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4
3 0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31
4 0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22
5 0x78,0x60,0x51,0x90 = add_a.d $w6, $w10, $w0
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s3 # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
4 # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
5 # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0]
6 # CHECK: add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90]
246 add_a.b $w26, $w9, $w4
247 add_a.h $w23, $w27, $w31
248 add_a.w $w11, $w6, $w22
249 add_a.d $w6, $w10, $w0
/external/llvm-project/llvm/test/MC/Mips/msa/
Dtest_3r.s3 # CHECK: add_a.b $w26, $w9, $w4 # encoding: [0x78,0x04,0x4e,0x90]
4 # CHECK: add_a.h $w23, $w27, $w31 # encoding: [0x78,0x3f,0xdd,0xd0]
5 # CHECK: add_a.w $w11, $w6, $w22 # encoding: [0x78,0x56,0x32,0xd0]
6 # CHECK: add_a.d $w6, $w10, $w0 # encoding: [0x78,0x60,0x51,0x90]
246 add_a.b $w26, $w9, $w4
247 add_a.h $w23, $w27, $w31
248 add_a.w $w11, $w6, $w22
249 add_a.d $w6, $w10, $w0
/external/flatbuffers/tests/
Darrays_test_generated.h260 void add_a(const MyGame::Example::ArrayStruct *a) { in add_a() function
279 builder_.add_a(a);
/external/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt3 0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4
4 0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31
5 0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22
6 0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0
/external/llvm-project/llvm/test/MC/Disassembler/Mips/msa/
Dtest_3r.txt3 0x78 0x04 0x4e 0x90 # CHECK: add_a.b $w26, $w9, $w4
4 0x78 0x3f 0xdd 0xd0 # CHECK: add_a.h $w23, $w27, $w31
5 0x78 0x56 0x32 0xd0 # CHECK: add_a.w $w11, $w6, $w22
6 0x78 0x60 0x51 0x90 # CHECK: add_a.d $w6, $w10, $w0
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Dloop-vectorization-factors.ll6 ; CHECK-LABEL: @add_a(
11 define void @add_a(i8* noalias nocapture readonly %p, i8* noalias nocapture %q, i32 %len) #0 {
/external/llvm-project/llvm/test/Transforms/LoopVectorize/AArch64/
Dloop-vectorization-factors.ll6 ; CHECK-LABEL: @add_a(
11 define void @add_a(i8* noalias nocapture readonly %p, i8* noalias nocapture %q, i32 %len) #0 {
/external/llvm-project/llvm/test/CodeGen/Mips/msa/
D3r-a.ll32 ; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
57 ; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
82 ; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
107 ; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
/external/llvm/test/CodeGen/Mips/msa/
D3r-a.ll32 ; CHECK-DAG: add_a.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
57 ; CHECK-DAG: add_a.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
82 ; CHECK-DAG: add_a.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
107 ; CHECK-DAG: add_a.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
/external/tensorflow/tensorflow/compiler/jit/
Dmark_for_compilation_pass_test.cc629 Output add_a = ops::Add(root.WithOpName("add_a"), switch_a.output_true, in TEST() local
633 Output add = ops::Add(root.WithOpName("add_c"), add_a, add_b); in TEST()
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1487 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1489 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1491 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1493 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1504 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1506 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1508 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1510 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td1504 class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
1506 class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
1508 class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
1510 class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4926 "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad"
5460 …{ 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
5461 …{ 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
5462 …{ 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
5463 …{ 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMF…
8349 { 61 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8350 { 69 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8351 { 77 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8352 { 85 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },