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Searched refs:avx512bf16 (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/X86/
Davx512bf16-intrinsics.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512bf16 --show-mc-encoding | FileCheck %s …
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bf16 --show-mc-encoding | FileCheck %…
5 declare <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float>, <16 x float>) #3
13 …%0 = tail call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %A, <16 x float> %B)…
31 …%0 = tail call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %A, <16 x float> %B)…
51 …%0 = tail call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %A, <16 x float> %B)…
59 declare <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float>) #3
67 %0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %A) #4
85 %0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %A) #4
105 %0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %A) #4
[all …]
Davx512bf16-vl-intrinsics.ll2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512bf16 -mattr=+avx512vl --show-mc-encodin…
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bf16 -mattr=+avx512vl --show-mc-encod…
5 declare <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float>, <4 x float>) #1
13 %0 = tail call <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float> %A, <4 x float> %B) #2
32 %0 = tail call <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float> %A, <4 x float> %B) #2
53 %0 = tail call <8 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.128(<4 x float> %A, <4 x float> %B) #2
61 declare <16 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.256(<8 x float>, <8 x float>) #3
69 …%0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.256(<8 x float> %A, <8 x float> %B) #4
87 …%0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.256(<8 x float> %A, <8 x float> %B) #4
107 …%0 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.256(<8 x float> %A, <8 x float> %B) #4
[all …]
Dstack-folding-avx512bf16.ll2 ; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512bf16,+avx512vl < %s …
22 %2 = call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %a0, <16 x float> %a1)
25 declare <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float>, <16 x float>)
40 %2 = call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %a0, <16 x float> %a1)
59 %2 = call <32 x i16> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %a0, <16 x float> %a1)
75 %2 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %a0)
78 declare <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float>)
93 %2 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %a0)
112 %2 = tail call <16 x i16> @llvm.x86.avx512bf16.cvtneps2bf16.512(<16 x float> %a0)
128 …%2 = tail call <16 x float> @llvm.x86.avx512bf16.dpbf16ps.512(<16 x float> %a0, <16 x i32> %a1, <1…
[all …]
/external/cpuinfo/include/
Dcpuinfo.h727 bool avx512bf16; member
1201 return cpuinfo_isa.avx512bf16; in cpuinfo_has_x86_avx512bf16()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/
DX86TargetParser.def164 X86_FEATURE_COMPAT(36, FEATURE_AVX512BF16, "avx512bf16")
/external/cpuinfo/src/x86/
Disa.c497 isa.avx512bf16 = avx512_regs && !!(structured_feature_info1.eax & UINT32_C(0x00000020)); in cpuinfo_x86_detect_isa()
/external/llvm-project/llvm/include/llvm/Support/
DX86TargetParser.def139 X86_FEATURE_COMPAT(AVX512BF16, "avx512bf16")
/external/llvm-project/clang/include/clang/Basic/
DBuiltinsX86.def1834 TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_128, "V8sV4fV4f", "ncV:128:", "avx512bf16,avx512vl")
1835 TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_256, "V16sV8fV8f", "ncV:256:", "avx512bf16,avx512vl")
1836 TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_512, "V32sV16fV16f", "ncV:512:", "avx512bf16")
1837 TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_128_mask, "V8sV4fV8sUc", "ncV:128:", "avx512bf16,avx512v…
1838 TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_256_mask, "V8sV8fV8sUc", "ncV:256:", "avx512bf16,avx512v…
1839 TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_512_mask, "V16sV16fV16sUs", "ncV:512:", "avx512bf16")
1840 TARGET_BUILTIN(__builtin_ia32_dpbf16ps_128, "V4fV4fV4iV4i", "ncV:128:", "avx512bf16,avx512vl")
1841 TARGET_BUILTIN(__builtin_ia32_dpbf16ps_256, "V8fV8fV8iV8i", "ncV:256:", "avx512bf16,avx512vl")
1842 TARGET_BUILTIN(__builtin_ia32_dpbf16ps_512, "V16fV16fV16iV16i", "ncV:512:", "avx512bf16")
1843 TARGET_BUILTIN(__builtin_ia32_cvtsbf162ss_32, "fUs", "nc", "avx512bf16")
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86.td171 def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true",
/external/llvm-project/llvm/lib/Target/X86/
DX86.td177 def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true",
/external/llvm-project/clang/docs/
DClangCommandLineReference.rst3232 .. option:: -mavx512bf16, -mno-avx512bf16
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicImpl.inc7112 "llvm.x86.avx512bf16.cvtne2ps2bf16.128",
7113 "llvm.x86.avx512bf16.cvtne2ps2bf16.256",
7114 "llvm.x86.avx512bf16.cvtne2ps2bf16.512",
7115 "llvm.x86.avx512bf16.cvtneps2bf16.256",
7116 "llvm.x86.avx512bf16.cvtneps2bf16.512",
7117 "llvm.x86.avx512bf16.dpbf16ps.128",
7118 "llvm.x86.avx512bf16.dpbf16ps.256",
7119 "llvm.x86.avx512bf16.dpbf16ps.512",
7120 "llvm.x86.avx512bf16.mask.cvtneps2bf16.128",
17245 1, // llvm.x86.avx512bf16.cvtne2ps2bf16.128
[all …]
/external/llvm-project/clang/include/clang/Driver/
DOptions.td3322 def mno_avx512bf16 : Flag<["-"], "mno-avx512bf16">, Group<m_x86_Features_Group>;
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenSubtargetInfo.inc170 …{ "avx512bf16", "Support bfloat16 floating point", X86::FeatureBF16, { { { 0x1000ULL, 0x0ULL, 0x0U…