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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td114 def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
138 def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;
147 def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
418 def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
419 def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
445 def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
446 def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
472 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
473 def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
474 def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
[all …]
DAArch64SVEInstrInfo.td197 defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", int_aarch64_sve_fmaxnm>;
317 defm ANDS_PPzPP : sve_int_pred_log<0b0100, "ands", null_frag>;
346 defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
392 defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
410 defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
428 defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>;
475 …defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw, AAr…
484 …defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw_scaled, …
497 …defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm, …
510 …defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm, …
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td119 def : DC<"ZVA", 0b011, 0b0111, 0b0100, 0b001>;
143 def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;
152 def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
423 def : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
424 def : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
450 def : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
451 def : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
477 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
478 def : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
479 def : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
[all …]
DAArch64SVEInstrInfo.td413 …defm FMAXNM_ZPmZ : sve_fp_2op_p_zds<0b0100, "fmaxnm", "FMAXNM_ZPZZ", int_aarch64_sve_fmaxnm, Destr…
645 defm ANDS_PPzPP : sve_int_pred_log<0b0100, "ands", null_frag>;
686 defm LD1SW_D_IMM : sve_mem_cld_si<0b0100, "ld1sw", Z_d, ZPR64>;
732 defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>;
750 defm LDNF1SW_D_IMM : sve_mem_cldnf_si<0b0100, "ldnf1sw", Z_d, ZPR64>;
768 defm LDFF1SW_D : sve_mem_cldff_ss<0b0100, "ldff1sw", Z_d, ZPR64, GPR64shifted32>;
815 …defm GLD1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw_z, A…
824 …defm GLD1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0100, "ld1sh", AArch64ld1s_gather_sxtw_scaled_z…
837 …defm GLD1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm_z,…
850 …defm GLD1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0100, "ld1sh", uimm5s2, AArch64ld1s_gather_imm_z,…
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td94 def : DC<"ZVA", 0b01, 0b011, 0b0111, 0b0100, 0b001>;
247 def : TLBI<"IPAS2E1", 0b01, 0b100, 0b1000, 0b0100, 0b001>;
248 def : TLBI<"IPAS2LE1", 0b01, 0b100, 0b1000, 0b0100, 0b101>;
341 def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
342 def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
372 def : ROSysReg<"TRCIDR12", 0b10, 0b001, 0b0000, 0b0100, 0b110>;
391 def : ROSysReg<"TRCPIDR4", 0b10, 0b001, 0b0111, 0b0100, 0b111>;
418 def : ROSysReg<"LORID_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b111>;
424 def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
460 def : RWSysReg<"DBGDTR_EL0", 0b10, 0b011, 0b0000, 0b0100, 0b000>;
[all …]
/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td229 def RET : IForm16<0b0100, DstReg, SrcPostInc, 2,
255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm),
258 def Br : I16rr<0b0100, (outs), (ins GR16:$rs),
261 def Bm : I16rm<0b0100, (outs), (ins memsrc:$src),
302 def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2,
319 def MOV8rr : I8rr<0b0100,
323 def MOV16rr : I16rr<0b0100,
330 def MOV8rc : I8rc<0b0100,
334 def MOV16rc : I16rc<0b0100,
338 def MOV8ri : I8ri<0b0100,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td229 def RET : IForm16<0b0100, DstReg, SrcPostInc, 2,
255 def Bi : I16ri<0b0100, (outs), (ins i16imm:$imm),
258 def Br : I16rr<0b0100, (outs), (ins GR16:$rs),
261 def Bm : I16rm<0b0100, (outs), (ins memsrc:$src),
302 def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2,
319 def MOV8rr : I8rr<0b0100,
323 def MOV16rr : I16rr<0b0100,
330 def MOV8rc : I8rc<0b0100,
334 def MOV16rc : I16rc<0b0100,
338 def MOV8ri : I8ri<0b0100,
[all …]
/external/llvm/test/MC/AsmParser/
Ddirective_values.s26 .quad 0b0100
/external/llvm-project/llvm/test/MC/AsmParser/
Ddirective_values.s26 .quad 0b0100
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h107 TT = 0b0100,
/external/llvm/lib/Target/Hexagon/
DHexagonSystemInst.td126 let Inst{27-24} = 0b0100;
/external/llvm-project/llvm/test/TableGen/
DDAGDefaultOps.td71 def MulIRR : RRI<"mul2", 0b0100> {
/external/llvm-project/llvm/lib/Target/RISCV/Utils/
DRISCVBaseInfo.h59 VMConstraint = 0b0100,
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt462 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
467 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt485 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
490 # VST2 multi-element, type == 0b0100, align == 0b11 -> undefined
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td278 defm : int_cond_alias<"leu", 0b0100>;
299 defm : fp_cond_alias<"l", 0b0100>;
322 defm : cp_cond_alias<"1", 0b0100>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td277 defm : int_cond_alias<"leu", 0b0100>;
298 defm : fp_cond_alias<"l", 0b0100>;
321 defm : cp_cond_alias<"1", 0b0100>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td277 defm : int_cond_alias<"leu", 0b0100>;
298 defm : fp_cond_alias<"l", 0b0100>;
321 defm : cp_cond_alias<"1", 0b0100>;
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td415 let Inst{11-8} = 0b0100;
520 let Inst{11-8} = 0b0100;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td416 let Inst{11-8} = 0b0100;
521 let Inst{11-8} = 0b0100;
/external/llvm-project/llvm/lib/Target/AVR/
DAVRInstrFormats.td434 let Inst{11-8} = 0b0100;
539 let Inst{11-8} = 0b0100;
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td886 let Inst{26-23} = 0b0100;
1129 let Inst{26-23} = 0b0100;
1147 let Inst{26-23} = 0b0100;
1163 let Inst{26-23} = 0b0100;
1181 let Inst{26-23} = 0b0100;
1194 let Inst{26-23} = 0b0100;
2166 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">;
2167 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">;
2168 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">;
2169 def t2USAX : T2I_pam<0b110, 0b0100, "usax">;
[all …]
DARMInstrNEON.td914 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
915 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
916 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
933 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
934 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
935 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
1084 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1119 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1916 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1917 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrFormats.td58 def VMConstraint : RISCVVConstraint<0b0100>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td649 class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
650 class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
708 class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
709 class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
828 class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
829 class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
830 class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
831 class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
935 class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
936 class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;

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