Home
last modified time | relevance | path

Searched refs:b1011 (Results 1 – 25 of 50) sorted by relevance

12

/external/llvm-project/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td835 def BIT8rr : I8rr<0b1011,
840 def BIT16rr : I16rr<0b1011,
846 def BIT8rc : I8rc<0b1011,
851 def BIT16rc : I16rc<0b1011,
857 def BIT8ri : I8ri<0b1011,
862 def BIT16ri : I16ri<0b1011,
868 def BIT8rm : I8rm<0b1011,
873 def BIT16rm : I16rm<0b1011,
879 def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
881 def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.td835 def BIT8rr : I8rr<0b1011,
840 def BIT16rr : I16rr<0b1011,
846 def BIT8rc : I8rc<0b1011,
851 def BIT16rc : I16rc<0b1011,
857 def BIT8ri : I8ri<0b1011,
862 def BIT16ri : I16ri<0b1011,
868 def BIT8rm : I8rm<0b1011,
873 def BIT16rm : I16rm<0b1011,
879 def BIT8rn : I8rn<0b1011, (outs), (ins GR8:$rd, indreg:$rs),
881 def BIT16rn : I16rn<0b1011, (outs), (ins GR16:$rd, indreg:$rs),
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td99 def : DC<"CVAU", 0b01, 0b011, 0b0111, 0b1011, 0b001>;
377 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
385 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
398 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
410 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
411 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
412 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
413 def : ROSysReg<"ICH_ELSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
445 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
446 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td119 def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;
629 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
637 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
650 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
662 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
663 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
664 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
665 def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
719 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
720 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td323 defm NAND_PPzPP : sve_int_pred_log<0b1011, "nand", int_aarch64_sve_nand_z>;
353 defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
399 defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
417 defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
435 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
480 …defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", null_frag, nul…
489 …defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", null_frag, …
502 …defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …
517 …defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, null_frag, …
534 …defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", null_frag, nxv2i32>;
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td124 def : DC<"CVAU", 0b011, 0b0111, 0b1011, 0b001>;
634 def : ROSysReg<"TRCIDR3", 0b10, 0b001, 0b0000, 0b1011, 0b111>;
642 def : ROSysReg<"TRCDEVAFF1", 0b10, 0b001, 0b0111, 0b1011, 0b110>;
655 def : ROSysReg<"TRCPIDR3", 0b10, 0b001, 0b0111, 0b1011, 0b111>;
667 def : ROSysReg<"ICC_RPR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b011>;
668 def : ROSysReg<"ICH_VTR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b001>;
669 def : ROSysReg<"ICH_EISR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b011>;
670 def : ROSysReg<"ICH_ELRSR_EL2", 0b11, 0b100, 0b1100, 0b1011, 0b101>;
724 def : WOSysReg<"ICC_DIR_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b001>;
725 def : WOSysReg<"ICC_SGI1R_EL1", 0b11, 0b000, 0b1100, 0b1011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td651 defm NAND_PPzPP : sve_int_pred_log<0b1011, "nand", int_aarch64_sve_nand_z>;
693 defm LD1W_D_IMM : sve_mem_cld_si<0b1011, "ld1w", Z_d, ZPR64>;
739 defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>;
757 defm LDNF1W_D_IMM : sve_mem_cldnf_si<0b1011, "ldnf1w", Z_d, ZPR64>;
775 defm LDFF1W_D : sve_mem_cldff_ss<0b1011, "ldff1w", Z_d, ZPR64, GPR64shifted32>;
820 …defm GLDFF1W : sve_mem_32b_gld_vs_32_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_z, A…
829 …defm GLDFF1W : sve_mem_32b_gld_sv_32_scaled<0b1011, "ldff1w", AArch64ldff1_gather_sxtw_scaled_…
842 …defm GLDFF1W : sve_mem_32b_gld_vi_32_ptrs<0b1011, "ldff1w", uimm5s4, AArch64ldff1_gather_imm_z…
857 …defm GLDFF1W_D : sve_mem_64b_gld_vi_64_ptrs<0b1011, "ldff1w", uimm5s4, AArch64ldff1_gather_imm_z…
874 …defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_z, nxv2i…
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td641 // Special case encoding: bits 11-8 is 0b1011.
657 let Inst{11-8} = 0b1011;
1032 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1085 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1254 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1293 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1390 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1430 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1473 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1494 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1296 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1309 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1337 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1349 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2290 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2303 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2329 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2341 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4230 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4252 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td1929 let Inst{7-4} = 0b1011;
2212 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2222 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2521 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2648 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2782 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2803 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
2941 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
2955 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3113 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td688 // Special case encoding: bits 11-8 is 0b1011.
705 let Inst{11-8} = 0b1011;
1121 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1178 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1357 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1403 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1507 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1554 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1603 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1628 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1304 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1317 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1345 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1357 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2359 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2372 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2398 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2410 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4383 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4408 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td2074 let Inst{7-4} = 0b1011;
2360 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2370 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2678 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2805 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
2939 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
2960 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3098 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3112 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3270 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td724 // Special case encoding: bits 11-8 is 0b1011.
741 let Inst{11-8} = 0b1011;
1190 def VMOVRRD : AVConv3I<0b11000101, 0b1011,
1247 def VMOVDRR : AVConv5I<0b11000100, 0b1011,
1435 def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1481 def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
1589 def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1636 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1685 def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
1710 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1286 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1299 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1327 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1339 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
2341 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2354 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2380 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2392 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
4314 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4339 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
[all …]
DARMInstrInfo.td2189 let Inst{7-4} = 0b1011;
2475 def BL : ABXI<0b1011, (outs), (ins arm_bl_target:$func),
2485 def BL_pred : ABI<0b1011, (outs), (ins arm_bl_target:$func),
2793 def LDRH : AI3ld<0b1011, 1, (outs GPR:$Rt), (ins addrmode3:$addr), LdMiscFrm,
2928 defm LDRH : AI3_ldridx<0b1011, "ldrh", IIC_iLoad_bh_ru>;
3065 defm LDRHT : AI3ldrT<0b1011, "ldrht">;
3086 def STRH : AI3str<0b1011, (outs), (ins GPR:$Rt, addrmode3:$addr), StMiscFrm,
3232 def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
3246 def STRH_POST : AI3ldstidx<0b1011, 0, 0, (outs GPR:$Rn_wb),
3404 defm STRHT : AI3strT<0b1011, "strht">;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h120 TETE = 0b1011
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td275 defm : int_cond_alias<"ge", 0b1011>;
305 defm : fp_cond_alias<"ge", 0b1011>;
328 defm : cp_cond_alias<"02", 0b1011>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td274 defm : int_cond_alias<"ge", 0b1011>;
304 defm : fp_cond_alias<"ge", 0b1011>;
327 defm : cp_cond_alias<"02", 0b1011>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td274 defm : int_cond_alias<"ge", 0b1011>;
304 defm : fp_cond_alias<"ge", 0b1011>;
327 defm : cp_cond_alias<"02", 0b1011>;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td384 let IClass = 0b1011;
1374 let Inst{27-24} = 0b1011;
1734 defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;
1929 defm loadruh : LD_PostInc <"memuh", "LDriuh", IntRegs, s4_1Imm, 0b1011>;
2016 def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
2080 def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
2165 def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
2268 def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
3371 defm storerf: ST_PostInc <"memh", "STrih_H", IntRegs, s4_1Imm, 0b1011, 1>;
3695 def S2_storerf_pci : T_store_pci<"memh", IntRegs, s4_1Imm, 0b1011,
[all …]
DHexagonInstrInfoV5.td163 let Inst{27-24} = 0b1011;
599 let Inst{27-24} = 0b1011;
/external/llvm/lib/Target/AVR/
DAVRInstrFormats.td419 let Inst{3-0} = 0b1011;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/
DAVRInstrFormats.td420 let Inst{3-0} = 0b1011;
/external/llvm-project/llvm/lib/Target/AVR/
DAVRInstrFormats.td438 let Inst{3-0} = 0b1011;

12