Home
last modified time | relevance | path

Searched refs:b1100 (Results 1 – 25 of 51) sorted by relevance

123

/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td317 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
318 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
357 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
358 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
359 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
360 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
378 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
399 def : ROSysReg<"TRCCIDR0", 0b10, 0b001, 0b0111, 0b1100, 0b111>;
406 def : ROSysReg<"ICC_IAR1_EL1", 0b11, 0b000, 0b1100, 0b1100, 0b000>;
407 def : ROSysReg<"ICC_IAR0_EL1", 0b11, 0b000, 0b1100, 0b1000, 0b000>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td124 def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
135 def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;
144 def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
559 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
560 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
608 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
609 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
610 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
611 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
630 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
[all …]
DAArch64SVEInstrInfo.td204 defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", int_aarch64_sve_fdivr>;
324 defm ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs", null_frag>;
354 defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
400 defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
418 defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
436 defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>;
1253 defm SQDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1100, "sqdmulh">;
1296 defm SMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1100, "smlslb">;
1381 defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
1638 defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext">;
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td129 def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
140 def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;
149 def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
564 def : ROSysReg<"PMCEID0_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b110>;
565 def : ROSysReg<"PMCEID1_EL0", 0b11, 0b011, 0b1001, 0b1100, 0b111>;
613 def : ROSysReg<"RVBAR_EL1", 0b11, 0b000, 0b1100, 0b0000, 0b001>;
614 def : ROSysReg<"RVBAR_EL2", 0b11, 0b100, 0b1100, 0b0000, 0b001>;
615 def : ROSysReg<"RVBAR_EL3", 0b11, 0b110, 0b1100, 0b0000, 0b001>;
616 def : ROSysReg<"ISR_EL1", 0b11, 0b000, 0b1100, 0b0001, 0b000>;
635 def : ROSysReg<"TRCIDR4", 0b10, 0b001, 0b0000, 0b1100, 0b111>;
[all …]
DAArch64SVEInstrInfo.td420 …defm FDIVR_ZPmZ : sve_fp_2op_p_zds<0b1100, "fdivr", "FDIVR_ZPZZ", int_aarch64_sve_fdivr, Destruct…
652 defm ORRS_PPzPP : sve_int_pred_log<0b1100, "orrs", null_frag>;
694 defm LD1SB_D_IMM : sve_mem_cld_si<0b1100, "ld1sb", Z_d, ZPR64>;
740 defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>;
758 defm LDNF1SB_D_IMM : sve_mem_cldnf_si<0b1100, "ldnf1sb", Z_d, ZPR64>;
776 defm LDFF1SB_D : sve_mem_cldff_ss<0b1100, "ldff1sb", Z_d, ZPR64, GPR64shifted8>;
2407 …defm SQDMULH_ZZZI : sve2_int_mul_by_indexed_elem<0b1100, "sqdmulh", int_aarch64_sve_sqdmulh_lane…
2467 …defm SMLSLB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1100, "smlslb", int_aarch64_sve_smlslb_lane…
2560 …defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr", "SRSHR_ZPZI", int_aarch64_s…
2822 defm BEXT_ZZZ : sve2_misc_bitwise<0b1100, "bext", int_aarch64_sve_bext_x>;
/external/mesa3d/src/panfrost/midgard/
Dmidgard_derivatives.c134 bool upper = ins->mask & 0b1100; in midgard_lower_derivatives()
147 dup.mask &= 0b1100; in midgard_lower_derivatives()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsMSAInstrFormats.td227 let Inst{21-18} = 0b1100;
279 let Inst{21-18} = 0b1100;
331 let Inst{21-18} = 0b1100;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrFormats.td227 let Inst{21-18} = 0b1100;
279 let Inst{21-18} = 0b1100;
331 let Inst{21-18} = 0b1100;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMSAInstrFormats.td227 let Inst{21-18} = 0b1100;
279 let Inst{21-18} = 0b1100;
331 let Inst{21-18} = 0b1100;
/external/llvm-project/llvm/lib/Target/ARM/Utils/
DARMBaseInfo.h108 TE = 0b1100,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrVFP.td821 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
829 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
837 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
845 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
853 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
868 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
1554 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1570 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1589 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1628 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1370 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1394 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1419 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1428 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1438 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1447 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
4386 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4435 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4437 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4597 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrVFP.td890 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
898 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
906 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
914 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
922 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
937 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
1636 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1652 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1671 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1710 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1352 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1376 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1401 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1410 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1420 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1429 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
4317 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4366 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4368 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4528 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt177 … qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
195 …To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td1475 let Inst{27-24} = 0b1100;
1738 defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
1934 defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
2017 def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
2086 def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
2172 def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
2271 def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
2326 let Inst{27-24} = 0b1100;
3365 defm storeri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm, 0b1100>;
3697 def S2_storeri_pci : T_store_pci<"memw", IntRegs, s4_2Imm, 0b1100,
[all …]
DHexagonInstrInfoV4.td178 let IClass = 0b1100;
429 def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
489 def L4_loadri_ur : T_LoadAbsReg<"memw", "LDriw", IntRegs, 0b1100>;
2006 let IClass = 0b1100;
2028 let IClass = 0b1100;
2052 let IClass = 0b1100;
2073 let IClass = 0b1100;
2339 let Inst{27-24} = 0b1100;
2583 let Inst{27-24} = 0b1100;
2707 let IClass = 0b1100;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td756 def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
764 def UH : AHuInp<0b11101, 0b11, 0b1100, 0b01, 0,
772 def SS : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
780 def US : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
788 def SD : ASuInp<0b11101, 0b11, 0b1100, 0b11, 0,
803 def UD : ASuInp<0b11101, 0b11, 0b1100, 0b01, 0,
1430 def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
1445 def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
1463 def VTOUIZH : AVConv1IsH_Encode<0b11101, 0b11, 0b1100, 0b1001,
1494 def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
[all …]
DARMInstrNEON.td1362 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1383 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1406 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1415 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1425 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1434 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
4233 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4276 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4278 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4436 defm VQRDMLSH : N3VInt3_HS<1, 0, 0b1100, 1, IIC_VMACi16D, IIC_VMACi32D,
[all …]
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt200 … qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
218 …To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td277 defm : int_cond_alias<"gu", 0b1100>;
306 defm : fp_cond_alias<"uge", 0b1100>;
329 defm : cp_cond_alias<"023", 0b1100>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td276 defm : int_cond_alias<"gu", 0b1100>;
305 defm : fp_cond_alias<"uge", 0b1100>;
328 defm : cp_cond_alias<"023", 0b1100>;
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrAliases.td276 defm : int_cond_alias<"gu", 0b1100>;
305 defm : fp_cond_alias<"uge", 0b1100>;
328 defm : cp_cond_alias<"023", 0b1100>;
/external/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td158 let Opcode = 0b1100;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrFormats.td157 let Opcode = 0b1100;

123