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Searched refs:before_inst (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/SPIRV-Tools/source/opt/
Dgraphics_robust_access_pass.h87 Instruction* value, Instruction* before_inst);
Dgraphics_robust_access_pass.cpp608 Instruction* before_inst) { in WidenInteger() argument
615 before_inst, (sign_extend ? SpvOpSConvert : SpvOpUConvert), type_id, in WidenInteger()
/external/angle/third_party/vulkan-deps/spirv-tools/src/source/opt/
Dgraphics_robust_access_pass.h87 Instruction* value, Instruction* before_inst);
Dgraphics_robust_access_pass.cpp609 Instruction* before_inst) { in WidenInteger() argument
616 before_inst, (sign_extend ? SpvOpSConvert : SpvOpUConvert), type_id, in WidenInteger()
/external/deqp-deps/SPIRV-Tools/source/opt/
Dgraphics_robust_access_pass.h87 Instruction* value, Instruction* before_inst);
Dgraphics_robust_access_pass.cpp608 Instruction* before_inst) { in WidenInteger() argument
615 before_inst, (sign_extend ? SpvOpSConvert : SpvOpUConvert), type_id, in WidenInteger()
/external/mesa3d/src/broadcom/compiler/
Dqpu_schedule.c1004 const struct v3d_qpu_instr *before_inst = &before->inst->qpu; in instruction_latency() local
1008 if (before_inst->type != V3D_QPU_INSTR_TYPE_ALU || in instruction_latency()
1012 if (before_inst->alu.add.magic_write) { in instruction_latency()
1014 magic_waddr_latency(before_inst->alu.add.waddr, in instruction_latency()
1018 if (before_inst->alu.mul.magic_write) { in instruction_latency()
1020 magic_waddr_latency(before_inst->alu.mul.waddr, in instruction_latency()
1024 if (v3d_qpu_instr_is_sfu(before_inst)) in instruction_latency()
/external/mesa3d/src/intel/compiler/
Dbrw_vec4_visitor.cpp736 vec4_instruction *before_inst) in emit_pull_constant_load_reg() argument
738 assert((before_inst == NULL && before_block == NULL) || in emit_pull_constant_load_reg()
739 (before_inst && before_block)); in emit_pull_constant_load_reg()
750 if (before_inst) in emit_pull_constant_load_reg()
751 emit_before(before_block, before_inst, pull); in emit_pull_constant_load_reg()
769 if (before_inst) in emit_pull_constant_load_reg()
770 emit_before(before_block, before_inst, pull); in emit_pull_constant_load_reg()
Dbrw_vec4.h299 vec4_instruction *before_inst);
/external/mesa3d/src/gallium/drivers/vc4/
Dvc4_qpu_schedule.c759 uint64_t before_inst = before->inst->inst; in instruction_latency() local
762 return MAX2(waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_ADD), in instruction_latency()
764 waddr_latency(QPU_GET_FIELD(before_inst, QPU_WADDR_MUL), in instruction_latency()