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Searched refs:buildCopy (Results 1 – 25 of 39) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Mips/
DMipsCallLowering.cpp146 auto Lo = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 0 : 1))); in assignValueToReg()
147 auto Hi = MIRBuilder.buildCopy(s32, Register(PhysReg + (IsEL ? 1 : 0))); in assignValueToReg()
152 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
159 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
164 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
247 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 0 : 1)), Unmerge.getReg(0)); in assignValueToReg()
248 MIRBuilder.buildCopy(Register(PhysReg + (IsEL ? 1 : 0)), Unmerge.getReg(1)); in assignValueToReg()
250 MIRBuilder.buildCopy(PhysReg, ValVReg); in assignValueToReg()
253 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
265 auto SPReg = MIRBuilder.buildCopy(p0, Register(Mips::SP)); in getStackAddress()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86CallLowering.cpp112 MIRBuilder.buildCopy(SPReg, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
146 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
274 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); in assignValueToReg()
279 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
285 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
DX86AvoidStoreForwardingBlocks.cpp108 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
384 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
/external/llvm-project/llvm/lib/Target/X86/
DX86CallLowering.cpp111 MIRBuilder.buildCopy(p0, STI.getRegisterInfo()->getStackRegister()); in getStackAddress()
144 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
272 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg); in assignValueToReg()
277 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
283 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
DX86AvoidStoreForwardingBlocks.cpp109 void buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, int64_t LoadDisp,
385 void X86AvoidSFBPass::buildCopy(MachineInstr *LoadInst, unsigned NLoadOpcode, in buildCopy() function in X86AvoidSFBPass
445 buildCopy(LoadInst, getYMMtoXMMLoadOpcode(LoadInst->getOpcode()), LdDisp, in buildCopies()
456 buildCopy(LoadInst, X86::MOV64rm, LdDisp, StoreInst, X86::MOV64mr, StDisp, in buildCopies()
466 buildCopy(LoadInst, X86::MOV32rm, LdDisp, StoreInst, X86::MOV32mr, StDisp, in buildCopies()
476 buildCopy(LoadInst, X86::MOV16rm, LdDisp, StoreInst, X86::MOV16mr, StDisp, in buildCopies()
486 buildCopy(LoadInst, X86::MOV8rm, LdDisp, StoreInst, X86::MOV8mr, StDisp, in buildCopies()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp62 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
101 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
110 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
115 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
331 B.buildCopy(ReturnAddrVReg, LiveInReturn); in lowerReturn()
416 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
596 B.buildCopy(LiveInReturn, ReturnAddrReg); in lowerFormalArguments()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64CallLowering.cpp76 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
81 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
157 MIRBuilder.buildCopy(SPReg, Register(AArch64::SP)); in getStackAddress()
173 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
366 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
412 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
888 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1014 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUCallLowering.cpp88 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
126 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg); in assignValueToReg()
135 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
140 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
222 SPReg = MIRBuilder.buildCopy(PtrTy, MFI->getStackPtrOffsetReg()).getReg(0); in getStackAddress()
235 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
490 B.buildCopy(ReturnAddrVReg, LiveInReturn); in lowerReturn()
568 B.buildCopy(VReg, InputPtrReg); in allocateHSAUserSGPRs()
808 B.buildCopy(LiveInReturn, ReturnAddrReg); in lowerFormalArguments()
1234 auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::vector(4, 32), in lowerCall()
[all …]
DAMDGPURegisterBankInfo.cpp860 OpReg = B.buildCopy(OpTy, OpReg).getReg(0); in executeInWaterfallLoop()
1108 Reg = B.buildCopy(Ty, Reg).getReg(0); in constrainOpWithReadfirstlane()
1274 auto SPCopy = B.buildCopy(PtrTy, SPReg); in applyMappingDynStackAlloc()
1401 VOffsetReg = B.buildCopy(S32, CombinedOffset).getReg(0); in setBufferOffsets()
1923 B.buildCopy(Hi32Reg, Lo32Reg); in extendLow32IntoHigh32()
1972 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldExtractEltToCmpSelect()
2008 B.buildCopy(DstReg, Res[L]); in foldExtractEltToCmpSelect()
2057 Idx = B.buildCopy(S32, Idx)->getOperand(0).getReg(); in foldInsertEltToCmpSelect()
2138 auto Copy = B.buildCopy(LLT::scalar(1), SrcReg); in applyMappingImpl()
2495 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64CallLowering.cpp75 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
80 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
156 SPReg = MIRBuilder.buildCopy(p0, Register(AArch64::SP)).getReg(0); in getStackAddress()
170 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
383 MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg); in lowerReturn()
429 MIRBuilder.buildCopy(Register(F.VReg), Register(F.PReg)); in handleMustTailForwardedRegisters()
912 MIRBuilder.buildCopy(ForwardedReg, Register(F.VReg)); in lowerTailCall()
1037 MIRBuilder.buildCopy(Info.SwiftErrorVReg, Register(AArch64::X21)); in lowerCall()
DAArch64InstructionSelector.cpp889 auto Copy = MIB.buildCopy({DstTempRC}, {SrcReg}); in selectCopy()
1934 auto NewSrc = MIB.buildCopy(LLT::scalar(64), I.getOperand(1).getReg()); in preISelLower()
2357 MIB.buildCopy({DefReg}, {LoadMI->getOperand(0).getReg()}); in select()
2367 MIB.buildCopy({DefReg}, {DefGPRReg}); in select()
3246 MIB.buildCopy(Register(AArch64::X0), LoadGOT.getReg(0)); in selectTLSGlobalValue()
3255 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0)); in selectTLSGlobalValue()
3537 MIB.buildCopy(DstReg, Cmp.getReg(0)); in selectVectorICmp()
4764 MIB.buildCopy(I.getOperand(0), CPLoad->getOperand(0)); in tryOptConstantBuildVec()
4913 MIRBuilder.buildCopy({SrcReg}, {I.getOperand(2)}); in selectIntrinsic()
4931 MIRBuilder.buildCopy({I.getOperand(0)}, {DstReg}); in selectIntrinsic()
[all …]
DAArch64PostLegalizerCombiner.cpp226 B.buildCopy(DstReg, Res.getReg(0)); in matchAArch64MulConstCombine()
/external/llvm-project/llvm/lib/Target/ARM/
DARMCallLowering.cpp101 auto SPReg = MIRBuilder.buildCopy(p0, Register(ARM::SP)); in getStackAddress()
120 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
346 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
353 auto PhysRegToVReg = MIRBuilder.buildCopy(LLT::scalar(LocSize), PhysReg); in assignValueToReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsCallLowering.cpp168 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg); in assignValueToReg()
173 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
282 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
295 MIRBuilder.buildCopy(SPReg, Register(Mips::SP)); in getStackAddress()
522 MIRBuilder.buildCopy(LLT::scalar(RegSize * 8), Register(ArgRegs[I])); in lowerFormalArguments()
632 MIRBuilder.buildCopy( in lowerCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMCallLowering.cpp103 MIRBuilder.buildCopy(SPReg, Register(ARM::SP)); in getStackAddress()
124 MIRBuilder.buildCopy(PhysReg, ExtReg); in assignValueToReg()
350 MIRBuilder.buildCopy(ValVReg, PhysReg); in assignValueToReg()
359 MIRBuilder.buildCopy(PhysRegToVReg, PhysReg); in assignValueToReg()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DIRTranslator.cpp349 MIRBuilder.buildCopy( in translateCompare()
352 MIRBuilder.buildCopy( in translateCompare()
881 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
926 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1036 MIRBuilder.buildCopy(Regs[0], SrcReg); in translateBitCast()
1119 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
1485 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
1499 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
1572 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallSite()
1787 MIRBuilder.buildCopy(ResRegs[0], ExceptionReg); in translateLandingPad()
[all …]
DCSEMIRBuilder.cpp132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg()); in generateCopiesIfRequired()
DCallLowering.cpp342 MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0)); in handleAssignments()
DCombinerHelper.cpp49 Builder.buildCopy(ToReg, FromReg); in replaceRegWith()
284 Builder.buildCopy(NewDstReg, Ops[0]); in applyCombineShuffleVector()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DInlineAsmLowering.cpp269 MIRBuilder.buildCopy(Dst, Src); in buildAnyextOrCopy()
630 MIRBuilder.buildCopy(Tmp1Reg, SrcReg); in lowerInlineAsm()
634 MIRBuilder.buildCopy(ResRegs[i], SrcReg); in lowerInlineAsm()
DIRTranslator.cpp336 MIRBuilder.buildCopy( in translateCompare()
339 MIRBuilder.buildCopy( in translateCompare()
1280 MIRBuilder.buildCopy(Regs[0], VReg); in translateLoad()
1324 MIRBuilder.buildCopy(VReg, Vals[0]); in translateStore()
1435 MIRBuilder.buildCopy(Regs[0], Src); in translateCopy()
1543 MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg); in translateGetElementPtr()
2068 MIRBuilder.buildCopy(Reg, StackPtr); in translateKnownIntrinsic()
2082 MIRBuilder.buildCopy(StackPtr, Reg); in translateKnownIntrinsic()
2112 MIRBuilder.buildCopy(getOrCreateVReg(CI), in translateKnownIntrinsic()
2235 MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt( in translateCallBase()
[all …]
DCSEMIRBuilder.cpp147 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
DCallLowering.cpp411 MIRBuilder.buildCopy(ArgReg, Unmerge.getReg(0)); in handleAssignments()
/external/llvm-project/llvm/lib/CodeGen/
DSplitKit.h442 SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DSplitKit.h434 SlotIndex buildCopy(unsigned FromReg, unsigned ToReg, LaneBitmask LaneMask,

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