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/external/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll41 ; M3: mov.s $f13, $f14
45 ; M3: mov.s $f0, $f13
58 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
62 ; SEL-64: sel.s $f0, $f14, $f13
82 ; M3: mov.s $f12, $f13
95 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
96 ; CMOV-64: mov.s $f0, $f13
99 ; SEL-64: sel.s $f0, $f13, $f12
114 ; M3: c.olt.s $f12, $f13
118 ; M3: mov.s $f12, $f13
[all …]
Dselect-dbl.ll63 ; M3: mov.d $f13, $f14
66 ; M3: mov.d $f0, $f13
69 ; CMOV-64: movn.d $f14, $f13, $[[T0]]
73 ; SEL-64: sel.d $f0, $f14, $f13
111 ; M3: mov.d $f12, $f13
117 ; CMOV-64: movn.d $f13, $f12, $[[T0]]
118 ; CMOV-64: mov.d $f0, $f13
121 ; SEL-64: sel.d $f0, $f13, $f12
137 ; M3: c.olt.d $f12, $f13
141 ; M3: mov.d $f12, $f13
[all …]
/external/deqp-deps/glslang/Test/
D100.frag46 float f13;
47 invariant f13; // ERROR
93 fwidth(f13); // ERROR
102 fwidth(f13);
103 gl_FragDepth = f13; // ERROR
104 gl_FragDepthEXT = f13; // ERROR
111 gl_FragDepth = f13; // ERROR
112 gl_FragDepthEXT = f13;
122 texture2DProj(sExt, vec3(f13));
134 texture3D(sExt, vec3(f13)); // ERROR
[all …]
/external/angle/third_party/vulkan-deps/glslang/src/Test/
D100.frag46 float f13;
47 invariant f13; // ERROR
93 fwidth(f13); // ERROR
102 fwidth(f13);
103 gl_FragDepth = f13; // ERROR
104 gl_FragDepthEXT = f13; // ERROR
111 gl_FragDepth = f13; // ERROR
112 gl_FragDepthEXT = f13;
122 texture2DProj(sExt, vec3(f13));
134 texture3D(sExt, vec3(f13)); // ERROR
[all …]
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll47 ; 64-C-DAG: c.eq.s $f12, $f13
54 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
64 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
81 ; 64-C-DAG: c.ule.s $f12, $f13
88 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
98 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
115 ; 64-C-DAG: c.ult.s $f12, $f13
122 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
132 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
149 ; 64-C-DAG: c.olt.s $f12, $f13
[all …]
Dno-odd-spreg-msa.ll14 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
17 ; Clobber all except $f12/$w12 and $f13
20 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
24 ; must copy $f13 to an even-numbered register before inserting into the
33 ; ALL: mov.s $f13, $f12
36 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
48 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
51 ; Clobber all except $f12/$w12 and $f13
54 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
58 ; must copy $f13 to an even-numbered register before inserting into the
[all …]
Dfmadd1.ll42 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
46 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
50 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
82 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
86 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
90 ; 64R6-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
125 ; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
127 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
131 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
133 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Dselect.ll149 ; 64: movn.s $f14, $f13, $4
152 ; 64R2: movn.s $f14, $f13, $4
157 ; 64R6: sel.s $[[CC]], $f14, $f13
185 ; 64: movn.d $f14, $f13, $4
188 ; 64R2: movn.d $f14, $f13, $4
193 ; 64R6: sel.d $[[CC]], $f14, $f13
222 ; 64: movt.s $f13, $f12, $fcc0
223 ; 64: mov.s $f0, $f13
226 ; 64R2: movt.s $f13, $f12, $fcc0
227 ; 64R2: mov.s $f0, $f13
[all …]
Dfpbr.ll13 ; 64-FCC: c.eq.s $f12, $f13
17 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
48 ; 64-FCC: c.olt.s $f12, $f13
52 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
78 ; 64-FCC: c.ole.s $f12, $f13
82 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
108 ; 64-FCC: c.eq.d $f12, $f13
112 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
139 ; 64-FCC: c.olt.d $f12, $f13
143 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Dno-odd-spreg.ll15 ; Clobber all except $f12 and $f13
18 ; allocator will choose $f12 and $f13 to avoid the spill/reload.
30 ; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}}
33 ; ODDSPREG: add.s $f0, $f12, $f13
42 ; Clobber all except $f12 and $f13
45 ; use $f12 and $f13.
/external/llvm-project/llvm/test/CodeGen/Mips/
Dno-odd-spreg-msa.ll14 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
17 ; Clobber all except $f12/$w12 and $f13
20 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
24 ; must copy $f13 to an even-numbered register before inserting into the
33 ; ALL: mov.s $f13, $f12
34 ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13
48 %b = call float asm sideeffect "mov.s $0, $1", "={$f13},{$f12}" (float %a)
51 ; Clobber all except $f12/$w12 and $f13
54 ; allocator will choose $f12/$w12 for the vector and $f13 for the float to
58 ; must copy $f13 to an even-numbered register before inserting into the
[all …]
Dfcmp.ll45 ; 64-C-DAG: c.eq.s $f12, $f13
52 ; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
78 ; 64-C-DAG: c.ule.s $f12, $f13
85 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
111 ; 64-C-DAG: c.ult.s $f12, $f13
118 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
144 ; 64-C-DAG: c.olt.s $f12, $f13
151 ; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
177 ; 64-C-DAG: c.ole.s $f12, $f13
184 ; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
[all …]
Dfmadd1.ll53 ; 64-DAG: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
57 ; 64R2: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
61 ; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
93 ; 64-DAG: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
97 ; 64R2: msub.s $[[T0:f[0-9]+]], $f14, $f12, $f13
101 ; 64R6-NOMADD-DAG: mul.s $[[T0:f[0-9]+]], $f12, $f13
136 ; 64-NONAN: nmadd.s $f0, $f14, $f12, $f13
138 ; 64-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
142 ; 64R2-NONAN: nmadd.s $f0, $f14, $f12, $f13
144 ; 64R2-NAN: madd.s $[[T0:f[0-9]+]], $f14, $f12, $f13
[all …]
Dfpbr.ll14 ; 64-FCC: c.eq.s $f12, $f13
18 ; 64-GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $f13
50 ; 64-FCC: c.olt.s $f12, $f13
54 ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12
81 ; 64-FCC: c.ole.s $f12, $f13
85 ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12
112 ; 64-FCC: c.eq.d $f12, $f13
116 ; 64-GPR: cmp.eq.d $[[FGRCC:f[0-9]+]], $f12, $f13
144 ; 64-FCC: c.olt.d $f12, $f13
148 ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12
[all …]
Dnmadd.ll18 ; CHECK-NM-64: nmadd.s $f0, $f14, $f12, $f13
21 ; CHECK-NOT-NM-64: mul.s $f0, $f12, $f13
36 ; CHECK-NM-64: nmadd.d $f0, $f14, $f12, $f13
39 ; CHECK-NOT-NM-64: mul.d $f0, $f12, $f13
54 ; CHECK-NM-64: nmsub.s $f0, $f14, $f12, $f13
57 ; CHECK-NOT-NM-64: mul.s $f0, $f12, $f13
72 ; CHECK-NM-64: nmsub.d $f0, $f14, $f12, $f13
75 ; CHECK-NOT-NM-64: mul.d $f0, $f12, $f13
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dselect-flt.ll74 ; M3-NEXT: mov.s $f0, $f13
86 ; CMOV64-NEXT: movn.s $f0, $f13, $1
92 ; 64R6-NEXT: sel.s $f0, $f14, $f13
152 ; M3-NEXT: mov.s $f0, $f13
159 ; CMOV64-NEXT: mov.s $f0, $f13
168 ; 64R6-NEXT: sel.s $f0, $f13, $f12
222 ; M3-NEXT: c.olt.s $f12, $f13
226 ; M3-NEXT: mov.s $f0, $f13
233 ; CMOV64-NEXT: mov.s $f0, $f13
234 ; CMOV64-NEXT: c.olt.s $f12, $f13
[all …]
Dselect-dbl.ll80 ; M3-NEXT: mov.d $f0, $f13
92 ; CMOV64-NEXT: movn.d $f0, $f13, $1
98 ; 64R6-NEXT: sel.d $f0, $f14, $f13
164 ; M3-NEXT: mov.d $f0, $f13
171 ; CMOV64-NEXT: mov.d $f0, $f13
180 ; 64R6-NEXT: sel.d $f0, $f13, $f12
238 ; M3-NEXT: c.olt.d $f12, $f13
242 ; M3-NEXT: mov.d $f0, $f13
249 ; CMOV64-NEXT: mov.d $f0, $f13
250 ; CMOV64-NEXT: c.olt.d $f12, $f13
[all …]
/external/webrtc/common_audio/third_party/ooura/fft_size_128/
Dooura_fft_mips.cc275 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cft1st_128_mips() local
515 [f12] "=&f"(f12), [f13] "=&f"(f13), [f14] "=&f"(f14), in cft1st_128_mips()
523 float f0, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14; in cftmdl_128_mips() local
631 f13 = rdft_wk3ri_first[2]; in cftmdl_128_mips()
714 [f12] "f"(f12), [f13] "f"(f13), [f14] "f"(f14) in cftmdl_128_mips()
718 f13 = rdft_wk3ri_second[2]; in cftmdl_128_mips()
872 [f12] "f"(f12), [f13] "f"(f13), [f14] "f"(f14) in cftmdl_128_mips()
996 float f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftfsub_128_mips() local
1109 [f13] "=&f"(f13), [f14] "=&f"(f14), [f15] "=&f"(f15), in rftfsub_128_mips()
1122 float f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15; in rftbsub_128_mips() local
[all …]
/external/llvm/test/MC/SystemZ/
Dregs-good.s63 #CHECK: ler %f12, %f13 # encoding: [0x38,0xcd]
72 ler %f12,%f13
81 #CHECK: ldr %f12, %f13 # encoding: [0x28,0xcd]
90 ldr %f12,%f13
96 #CHECK: lxr %f12, %f13 # encoding: [0xb3,0x65,0x00,0xcd]
101 lxr %f12,%f13
132 #CHECK: .cfi_offset %f13, 232
166 .cfi_offset %f13,232
/external/libffi/testsuite/libffi.call/
Dmany.c14 …t f4, float f5, float f6, float f7, float f8, float f9, float f10, float f11, float f12, float f13) in many() argument
20 (double) f11, (double) f12, (double) f13); in many()
23 return f1+f2+f3+f4+f5+f6+f7+f8+f9+f10+f11+f12+f13; in many()
Dmany_double.c26 double f13) in many() argument
32 (double) f11, (double) f12, (double) f13); in many()
35 return ((f1/f2+f3/f4+f5/f6+f7/f8+f9/f10+f11/f12) * f13); in many()
/external/python/cpython2/Modules/_ctypes/libffi/testsuite/libffi.call/
Dmany.c14 …t f4, float f5, float f6, float f7, float f8, float f9, float f10, float f11, float f12, float f13) in many() argument
20 (double) f11, (double) f12, (double) f13); in many()
23 return f1+f2+f3+f4+f5+f6+f7+f8+f9+f10+f11+f12+f13; in many()
/external/capstone/suite/MC/SystemZ/
Dregs-good.s.cs32 0x38,0xcd = ler %f12, %f13
40 0x28,0xcd = ldr %f12, %f13
45 0xb3,0x65,0x00,0xcd = lxr %f12, %f13
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Danyregcc-novec.ll22 ;CHECK: std %f13,
33 …f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15}"() n…
48 ;CHECK-NEXT: std %f13,
65 %a13 = call double asm sideeffect "", "={f13}"() nounwind
69 … "", "{f0},{f1},{f2},{f3},{f4},{f5},{f6},{f7},{f8},{f9},{f10},{f11},{f12},{f13},{f14},{f15}"(doubl…
/external/llvm-project/llvm/test/MC/SystemZ/
Dinsn-good-z196.s231 #CHECK: axtra %f0, %f0, %f13, 0 # encoding: [0xb3,0xda,0xd0,0x00]
232 #CHECK: axtra %f0, %f13, %f0, 0 # encoding: [0xb3,0xda,0x00,0x0d]
233 #CHECK: axtra %f13, %f0, %f0, 0 # encoding: [0xb3,0xda,0x00,0xd0]
238 axtra %f0, %f0, %f13, 0
239 axtra %f0, %f13, %f0, 0
240 axtra %f13, %f0, %f0, 0
492 #CHECK: cfxbra %r0, 0, %f13, 0 # encoding: [0xb3,0x9a,0x00,0x0d]
499 cfxbra %r0, 0, %f13, 0
506 #CHECK: cfxtr %r0, 0, %f13, 0 # encoding: [0xb9,0x49,0x00,0x0d]
513 cfxtr %r0, 0, %f13, 0
[all …]

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