| /external/llvm-project/llvm/test/MC/RISCV/ |
| D | rvf-user-csr-names.s | 55 # fcsr
57 # CHECK-INST: csrrs t1, fcsr, zero
60 # CHECK-INST-ALIAS-NO-F: csrr t1, fcsr
62 # CHECK-INST: csrrs t2, fcsr, zero
65 # CHECK-INST-ALIAS-NO-F: csrr t2, fcsr
67 csrrs t1, fcsr, zero
|
| D | csr-aliases.s | 40 # CHECK-INST: csrrs t0, fcsr, zero
43 # CHECK-EXT-F-OFF: csrr t0, fcsr
46 # CHECK-INST: csrrw t1, fcsr, t2
49 # CHECK-EXT-F-OFF: csrrw t1, fcsr, t2
52 # CHECK-INST: csrrw zero, fcsr, t2
55 # CHECK-EXT-F-OFF: csrw fcsr, t2
58 # CHECK-INST: csrrw zero, fcsr, t2
61 # CHECK-EXT-F-OFF: csrw fcsr, t2
|
| D | rvf-aliases-valid.s | 48 # CHECK-INST: csrrs t0, fcsr, zero
51 # CHECK-INST: csrrw t1, fcsr, t2
54 # CHECK-INST: csrrw zero, fcsr, t3
60 # CHECK-INST: csrrs t4, fcsr, zero
63 # CHECK-INST: csrrw t5, fcsr, t6
66 # CHECK-INST: csrrw zero, fcsr, s0
|
| /external/rust/crates/gdbstub/src/arch/mips/reg/ |
| D | mips.rs | 50 pub fcsr: U, field
133 write_le_bytes!(&self.fpu.fcsr); in gdb_serialize()
175 self.fpu.fcsr = regs.next().ok_or(())?; in gdb_deserialize()
|
| /external/llvm-project/lldb/source/Plugins/Instruction/MIPS64/ |
| D | EmulateInstructionMIPS64.cpp | 1981 uint32_t cc, fcsr; in Emulate_FP_branch() local
1999 fcsr = in Emulate_FP_branch()
2005 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2008 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2013 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2106 uint32_t cc, fcsr; in Emulate_3D_branch() local
2117 fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips64, in Emulate_3D_branch()
2123 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2127 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2133 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
[all …]
|
| /external/llvm-project/lldb/source/Plugins/Instruction/MIPS/ |
| D | EmulateInstructionMIPS.cpp | 2678 uint32_t cc, fcsr; in Emulate_FP_branch() local
2689 fcsr = ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0, &success); in Emulate_FP_branch()
2694 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_FP_branch()
2697 if ((fcsr & (1 << cc)) == 0) in Emulate_FP_branch()
2702 if ((fcsr & (1 << cc)) != 0) in Emulate_FP_branch()
2794 uint32_t cc, fcsr; in Emulate_3D_branch() local
2805 fcsr = (uint32_t)ReadRegisterUnsigned(eRegisterKindDWARF, dwarf_fcsr_mips, 0, in Emulate_3D_branch()
2811 fcsr = ((fcsr >> 24) & 0xfe) | ((fcsr >> 23) & 0x01); in Emulate_3D_branch()
2815 if (((fcsr >> cc) & 3) != 3) in Emulate_3D_branch()
2821 if (((fcsr >> cc) & 3) != 0) in Emulate_3D_branch()
[all …]
|
| /external/llvm-project/lldb/source/Plugins/Process/Utility/ |
| D | RegisterContext_mips.h | 319 uint32_t fcsr; member
361 uint32_t fcsr; /* FPU control status register */ member
|
| D | RegisterInfos_mips.h | 211 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
285 DEFINE_MSA_INFO(fcsr, nullptr, dwarf_fcsr_mips, dwarf_fcsr_mips,
|
| D | RegisterInfos_mips64.h | 337 DEFINE_FPR_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
411 DEFINE_MSA_INFO(fcsr, nullptr, dwarf_fcsr_mips64, dwarf_fcsr_mips64,
|
| /external/llvm-project/compiler-rt/test/asan/TestCases/Linux/ |
| D | ptrace.cpp | 75 #define PRINT_REG_FP(__fpregs) printf("%lx\n", (unsigned long)(__fpregs.fcsr))
|
| /external/llvm-project/lldb/source/Plugins/Process/Linux/ |
| D | NativeRegisterContextLinux_mips64.cpp | 485 m_fpr.fcsr = m_msa.fcsr; in ReadCP1()
531 m_msa.fcsr = m_fpr.fcsr; in WriteCP1()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVSystemOperands.td | 76 def FCSR : SysReg<"fcsr", 0x003>;
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVSystemOperands.td | 83 def FCSR : SysReg<"fcsr", 0x003>;
|