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Searched refs:fcvtnu (Results 1 – 25 of 55) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s156 fcvtnu h12, h13
157 fcvtnu s12, s13
158 fcvtnu d21, d14
Darm64-fp-encoding.s344 fcvtnu w1, h2
345 fcvtnu w1, s2
346 fcvtnu w1, d2
347 fcvtnu x1, h2
348 fcvtnu x1, s2
349 fcvtnu x1, d2
351 ; FP16: fcvtnu w1, h2 ; encoding: [0x41,0x00,0xe1,0x1e]
353 ; NO-FP16-NEXT: fcvtnu w1, h2
354 ; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
355 ; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
[all …]
Dneon-simd-misc.s561 fcvtnu v4.4h, v0.4h
562 fcvtnu v6.8h, v8.8h
563 fcvtnu v6.4s, v8.4s
564 fcvtnu v6.2d, v8.2d
565 fcvtnu v4.2s, v0.2s
Dfullfp16-neon-neg.s240 fcvtnu h12, h13
334 fcvtnu v4.4h, v0.4h
336 fcvtnu v6.8h, v8.8h
Darm64-advsimd.s850 fcvtnu.2s v0, v0
851 fcvtnu.4s v0, v0
852 fcvtnu.2d v0, v0
853 fcvtnu s0, s0
854 fcvtnu d0, d0 define
856 ; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e]
857 ; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e]
858 ; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e]
859 ; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e]
860 ; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
Dneon-diagnostics.s5896 fcvtnu v0.16b, v31.16b
5897 fcvtnu v2.8h, v4.8h
5898 fcvtnu v1.8b, v9.8b
5899 fcvtnu v13.4h, v21.4h
7252 fcvtnu s0, d0
7253 fcvtnu d0, s0 define
/external/llvm-project/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s156 fcvtnu h12, h13
157 fcvtnu s12, s13
158 fcvtnu d21, d14
Darm64-fp-encoding.s344 fcvtnu w1, h2
345 fcvtnu w1, s2
346 fcvtnu w1, d2
347 fcvtnu x1, h2
348 fcvtnu x1, s2
349 fcvtnu x1, d2
351 ; FP16: fcvtnu w1, h2 ; encoding: [0x41,0x00,0xe1,0x1e]
353 ; NO-FP16-NEXT: fcvtnu w1, h2
354 ; CHECK: fcvtnu w1, s2 ; encoding: [0x41,0x00,0x21,0x1e]
355 ; CHECK: fcvtnu w1, d2 ; encoding: [0x41,0x00,0x61,0x1e]
[all …]
Dneon-simd-misc.s561 fcvtnu v4.4h, v0.4h
562 fcvtnu v6.8h, v8.8h
563 fcvtnu v6.4s, v8.4s
564 fcvtnu v6.2d, v8.2d
565 fcvtnu v4.2s, v0.2s
Dfullfp16-neon-neg.s240 fcvtnu h12, h13
334 fcvtnu v4.4h, v0.4h
336 fcvtnu v6.8h, v8.8h
Darm64-advsimd.s850 fcvtnu.2s v0, v0
851 fcvtnu.4s v0, v0
852 fcvtnu.2d v0, v0
853 fcvtnu s0, s0
854 fcvtnu d0, d0 define
856 ; CHECK: fcvtnu.2s v0, v0 ; encoding: [0x00,0xa8,0x21,0x2e]
857 ; CHECK: fcvtnu.4s v0, v0 ; encoding: [0x00,0xa8,0x21,0x6e]
858 ; CHECK: fcvtnu.2d v0, v0 ; encoding: [0x00,0xa8,0x61,0x6e]
859 ; CHECK: fcvtnu s0, s0 ; encoding: [0x00,0xa8,0x21,0x7e]
860 ; CHECK: fcvtnu d0, d0 ; encoding: [0x00,0xa8,0x61,0x7e]
Dneon-diagnostics.s5836 fcvtnu v0.16b, v31.16b
5837 fcvtnu v2.8h, v4.8h
5838 fcvtnu v1.8b, v9.8b
5839 fcvtnu v13.4h, v21.4h
7021 fcvtnu s0, d0
7022 fcvtnu d0, s0 define
Dbasic-a64-instructions.s2053 fcvtnu wzr, s12
2054 fcvtnu x0, s0
2107 fcvtnu wzr, d12
2108 fcvtnu x0, d0
/external/llvm-project/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll208 ;CHECK: fcvtnu w0, s0
210 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A)
216 ;CHECK: fcvtnu x0, s0
218 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)
224 ;CHECK: fcvtnu w0, d0
226 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)
232 ;CHECK: fcvtnu x0, d0
234 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A)
238 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone
239 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone
[all …]
Dfp16_intrinsic_scalar_1op.ll7 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half)
8 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half)
278 ; CHECK: fcvtnu w0, h0
281 %fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a)
288 ; CHECK: fcvtnu x0, h0
291 %vcvtnh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)
Darm64-vcvt.ll299 ;CHECK: fcvtnu.2s v0, v0
301 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)
308 ;CHECK: fcvtnu.4s v0, v0
310 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)
317 ;CHECK: fcvtnu.2d v0, v0
319 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)
326 ;CHECK: fcvtnu d0, d0
328 %tmp3 = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %A)
332 declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
333 declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-cvt.ll208 ;CHECK: fcvtnu w0, s0
210 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A)
216 ;CHECK: fcvtnu x0, s0
218 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)
224 ;CHECK: fcvtnu w0, d0
226 %tmp3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)
232 ;CHECK: fcvtnu x0, d0
234 %tmp3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A)
238 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone
239 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone
[all …]
Darm64-vcvt.ll223 ;CHECK: fcvtnu.2s v0, v0
225 %tmp3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)
232 ;CHECK: fcvtnu.4s v0, v0
234 %tmp3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)
241 ;CHECK: fcvtnu.2d v0, v0
243 %tmp3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)
247 declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone
248 declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone
249 declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone
/external/capstone/suite/MC/AArch64/
Dneon-scalar-cvt.s.cs25 0xac,0xa9,0x21,0x7e = fcvtnu s12, s13
26 0xd5,0xa9,0x61,0x7e = fcvtnu d21, d14
Dneon-simd-misc.s.cs168 0x06,0xa9,0x21,0x6e = fcvtnu v6.4s, v8.4s
169 0x06,0xa9,0x61,0x6e = fcvtnu v6.2d, v8.2d
170 0x04,0xa8,0x21,0x2e = fcvtnu v4.2s, v0.2s
Dbasic-a64-instructions.s.cs807 0x9f,0x01,0x21,0x1e = fcvtnu wzr, s12
808 0x00,0x00,0x21,0x9e = fcvtnu x0, s0
831 0x9f,0x01,0x61,0x1e = fcvtnu wzr, d12
832 0x00,0x00,0x61,0x9e = fcvtnu x0, d0
/external/vixl/test/aarch64/
Dtest-disasm-fp-aarch64.cc284 COMPARE(fcvtnu(w8, s9), "fcvtnu w8, s9"); in TEST()
285 COMPARE(fcvtnu(x10, s11), "fcvtnu x10, s11"); in TEST()
286 COMPARE(fcvtnu(w12, d13), "fcvtnu w12, d13"); in TEST()
287 COMPARE(fcvtnu(x14, d15), "fcvtnu x14, d15"); in TEST()
354 COMPARE(fcvtnu(w8, h9), "fcvtnu w8, h9"); in TEST()
355 COMPARE(fcvtnu(x10, h11), "fcvtnu x10, h11"); in TEST()
Dtest-cpu-features-aarch64.cc569 TEST_FP(fcvtnu_0, fcvtnu(w0, d1))
570 TEST_FP(fcvtnu_1, fcvtnu(w0, s1))
571 TEST_FP(fcvtnu_2, fcvtnu(x0, d1))
572 TEST_FP(fcvtnu_3, fcvtnu(x0, s1))
3201 TEST_FP_NEON(fcvtnu_0, fcvtnu(v0.V2S(), v1.V2S()))
3202 TEST_FP_NEON(fcvtnu_1, fcvtnu(v0.V4S(), v1.V4S()))
3203 TEST_FP_NEON(fcvtnu_2, fcvtnu(v0.V2D(), v1.V2D()))
3204 TEST_FP_NEON(fcvtnu_3, fcvtnu(s0, s1))
3205 TEST_FP_NEON(fcvtnu_4, fcvtnu(d0, d1))
3467 TEST_FP_FPHALF(fcvtnu_0, fcvtnu(w0, h1))
[all …]
Dtest-trace-aarch64.cc478 __ fcvtnu(d0, d21); in GenerateTestSequenceFP() local
479 __ fcvtnu(s6, s25); in GenerateTestSequenceFP() local
480 __ fcvtnu(w29, d11); in GenerateTestSequenceFP() local
481 __ fcvtnu(w25, s31); in GenerateTestSequenceFP() local
482 __ fcvtnu(x30, d11); in GenerateTestSequenceFP() local
483 __ fcvtnu(x27, s18); in GenerateTestSequenceFP() local
2588 __ fcvtnu(v18.V2D(), v27.V2D()); in GenerateTestSequenceNEONFP() local
2589 __ fcvtnu(v11.V2S(), v14.V2S()); in GenerateTestSequenceNEONFP() local
2590 __ fcvtnu(v27.V4S(), v21.V4S()); in GenerateTestSequenceNEONFP() local
/external/llvm-project/llvm/test/tools/llvm-mca/AArch64/Cortex/
DA55-basic-instructions.s747 fcvtnu wzr, h12 label
748 fcvtnu x0, h0 label
771 fcvtnu wzr, s12 label
772 fcvtnu x0, s0 label
795 fcvtnu wzr, d12 label
796 fcvtnu x0, d0 label
2019 # CHECK-NEXT: 1 3 0.50 fcvtnu wzr, h12
2020 # CHECK-NEXT: 1 3 0.50 fcvtnu x0, h0
2043 # CHECK-NEXT: 1 3 0.50 fcvtnu wzr, s12
2044 # CHECK-NEXT: 1 3 0.50 fcvtnu x0, s0
[all …]

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