| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUGlobalISelUtils.cpp | 18 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); in getBaseWithConstantOffset()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUGlobalISelUtils.cpp | 18 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); in getBaseWithConstantOffset()
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| D | AMDGPUInstructionSelector.cpp | 626 MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI); in selectG_BUILD_VECTOR_TRUNC()
1323 MachineInstr *OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI); in selectDSGWSIntrinsic()
1339 OffsetDef = getDefIgnoringCopies(BaseOffset, *MRI); in selectDSGWSIntrinsic()
3170 MachineInstr *MI = getDefIgnoringCopies(Src, *MRI); in selectVOP3ModsImpl()
3175 MI = getDefIgnoringCopies(Src, *MRI); in selectVOP3ModsImpl()
3274 const MachineInstr *Def = getDefIgnoringCopies(Reg, *MRI); in selectVOP3NoMods()
3473 const MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); in matchZeroExtendFromS32()
3852 MachineInstr *RootI = getDefIgnoringCopies(Root, MRI); in getPtrBaseWithConstantOffset()
3955 Data.N2 = getDefIgnoringCopies(Data.N2, *MRI)->getOperand(0).getReg(); in parseMUBUFAddress()
3956 Data.N3 = getDefIgnoringCopies(Data.N3, *MRI)->getOperand(0).getReg(); in parseMUBUFAddress()
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| D | AMDGPURegisterBankInfo.cpp | 1316 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); in getSrcRegIgnoringCopies()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 144 MachineInstr *getDefIgnoringCopies(Register Reg,
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| D | LegalizationArtifactCombiner.h | 290 getDefIgnoringCopies(MI.getOperand(NumDefs).getReg(), MRI); in tryCombineMerges()
303 MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI); in tryCombineMerges()
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | Utils.h | 168 MachineInstr *getDefIgnoringCopies(Register Reg,
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| D | LegalizationArtifactCombiner.h | 529 MachineInstr *SrcDef = getDefIgnoringCopies(SrcReg, MRI); in tryCombineUnmergeValues()
588 MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI); in tryCombineUnmergeValues()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 303 llvm::MachineInstr *llvm::getDefIgnoringCopies(Register Reg, in getDefIgnoringCopies() function in llvm
321 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef()
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| D | CombinerHelper.cpp | 678 MachineInstr *BaseDef = getDefIgnoringCopies(Base, MRI); in findPreIndexCandidate()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 372 MachineInstr *llvm::getDefIgnoringCopies(Register Reg, in getDefIgnoringCopies() function in llvm
388 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef()
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| D | CombinerHelper.cpp | 778 MachineInstr *BaseDef = getDefIgnoringCopies(Base, MRI); in findPreIndexCandidate()
2459 MachineInstr *I1 = getDefIgnoringCopies(MOP1.getReg(), MRI); in matchEqualDefs()
2462 MachineInstr *I2 = getDefIgnoringCopies(MOP2.getReg(), MRI); in matchEqualDefs()
2719 MachineInstr *LeftHandInst = getDefIgnoringCopies(LHSReg, MRI); in matchHoistLogicOpWithSameOpcodeHands()
2720 MachineInstr *RightHandInst = getDefIgnoringCopies(RHSReg, MRI); in matchHoistLogicOpWithSameOpcodeHands()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 1346 MachineInstr *Def = getDefIgnoringCopies(I.getOperand(0).getReg(), MRI); in contractCrossBankCopyIntoStore()
3612 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI); in tryFoldIntegerCompare()
3613 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI); in tryFoldIntegerCompare()
4357 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
4417 getDefIgnoringCopies(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeShiftedExtendXReg()
4502 MachineInstr *OffsetInst = getDefIgnoringCopies(RHS.getReg(), MRI); in selectAddrModeWRO()
4798 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI); in selectArithExtendedRegister()
4817 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI); in selectArithExtendedRegister()
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| D | AArch64CallLowering.cpp | 640 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in areCalleeOutgoingArgsTailCallable()
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| /external/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 1265 while (MachineInstr *MI = getDefIgnoringCopies(Reg, MRI)) { in getTestBitReg()
4468 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI); in tryFoldIntegerCompare()
4469 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI); in tryFoldIntegerCompare()
5226 MachineInstr *ExtInst = getDefIgnoringCopies(OffsetReg, MRI); in selectExtendedSHL()
5290 getDefIgnoringCopies(PtrAdd->getOperand(2).getReg(), MRI); in selectAddrModeShiftedExtendXReg()
5423 MachineInstr *OffsetInst = getDefIgnoringCopies(RHS.getReg(), MRI); in selectAddrModeWRO()
5763 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI); in selectArithExtendedRegister()
5782 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI); in selectArithExtendedRegister()
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| D | AArch64CallLowering.cpp | 665 MachineInstr *RegDef = getDefIgnoringCopies(OutInfo.Regs[0], MRI); in areCalleeOutgoingArgsTailCallable()
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