| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 51 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
52 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg); in run()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SILowerSGPRSpills.cpp | 103 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSaves()
136 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRRestores()
209 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegs()
|
| D | GCNRegBankReassign.cpp | 281 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getPhysRegBank()
308 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getRegBankMask()
442 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); in isReassignable()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SILowerSGPRSpills.cpp | 105 TRI->getMinimalPhysRegClass(Reg, MVT::i32); in insertCSRSaves()
139 TRI->getMinimalPhysRegClass(Reg, MVT::i32); in insertCSRRestores()
213 TRI->getMinimalPhysRegClass(Reg, MVT::i32); in spillCalleeSavedRegs()
|
| D | GCNRegBankReassign.cpp | 305 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getPhysRegBank()
342 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in getRegBankMask()
495 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg); in isReassignable()
|
| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
|
| D | WebAssemblyInstrInfo.cpp | 61 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
|
| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyReplacePhysRegs.cpp | 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); in runOnMachineFunction()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 47 if (TRI.getMinimalPhysRegClass(DstR.Reg) != in interpretAsCopy()
48 TRI.getMinimalPhysRegClass(SrcR.Reg)) in interpretAsCopy()
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 88 return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT()); in getRegBank()
101 RegisterBankInfo::getMinimalPhysRegClass(Register Reg, in getMinimalPhysRegClass() function in RegisterBankInfo
107 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg); in getMinimalPhysRegClass()
502 auto *RC = &getMinimalPhysRegClass(Reg, TRI); in getSizeInBits()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 88 return &getRegBankFromRegClass(getMinimalPhysRegClass(Reg, TRI), LLT()); in getRegBank()
101 RegisterBankInfo::getMinimalPhysRegClass(Register Reg, in getMinimalPhysRegClass() function in RegisterBankInfo
107 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg); in getMinimalPhysRegClass()
502 auto *RC = &getMinimalPhysRegClass(Reg, TRI); in getSizeInBits()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 122 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize(); in estimateStackSize()
|
| /external/llvm-project/llvm/test/CodeGen/AVR/ |
| D | pre-schedule.ll | 24 …:203: const llvm::TargetRegisterClass* llvm::TargetRegisterInfo::getMinimalPhysRegClass(unsigned i…
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | FixupStatepointCallerSaved.cpp | 97 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in getRegisterSize()
407 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in spillRegisters()
428 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in insertReloadBefore()
|
| D | TargetRegisterInfo.cpp | 210 TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
497 RC = getMinimalPhysRegClass(Reg); in getRegSizeInBits()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 812 if (TRI->getMinimalPhysRegClass(OriginalReg) == in mergePairedInsns()
813 TRI->getMinimalPhysRegClass(SubOrSuper)) in mergePairedInsns()
1275 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef()
1294 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef()
1359 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1373 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1416 return C == TRI->getMinimalPhysRegClass(SubOrSuper); in tryToFindRegisterToRename()
1421 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename()
|
| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in PrintAsmOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg); in PrintAsmOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 190 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, MVT VT) const { in getMinimalPhysRegClass() function in TargetRegisterInfo
479 RC = getMinimalPhysRegClass(Reg); in getRegSizeInBits()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 812 if (TRI->getMinimalPhysRegClass(OriginalReg) == in mergePairedInsns()
813 TRI->getMinimalPhysRegClass(SubOrSuper)) in mergePairedInsns()
1286 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef()
1354 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1368 RequiredClasses.insert(TRI->getMinimalPhysRegClass(MOP.getReg())); in canRenameUpToDef()
1411 return C == TRI->getMinimalPhysRegClass(SubOrSuper); in tryToFindRegisterToRename()
1416 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVMCInstLower.cpp | 170 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in lowerRISCVVMachineInstrToMCInst()
|