| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 48 const TargetInstrInfo &getTII() { in getTII() function
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsCallLowering.cpp | 152 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in assignValueToReg()
160 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in assignValueToReg()
264 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in assignValueToReg()
272 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in assignValueToReg()
278 .constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in assignValueToReg()
641 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
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| D | MipsLegalizerInfo.cpp | 294 Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in legalizeCustom()
325 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 60 MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode)); in buildInstr()
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| /external/llvm/lib/Target/Hexagon/ |
| D | RDFCopy.cpp | 61 const TargetInstrInfo &TII = DFG.getTII(); in interpretAsCopy()
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| D | HexagonRDFOpt.cpp | 206 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
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| D | RDFGraph.h | 618 const TargetInstrInfo &getTII() const { in getTII() function
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| D | RDFGraph.cpp | 212 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc) in operator <<()
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRDFOpt.cpp | 220 auto &HII = static_cast<const HexagonInstrInfo&>(DFG.getTII()); in rewrite()
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| D | RDFGraph.h | 662 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
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| D | RDFGraph.cpp | 227 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 79 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert()
98 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
111 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
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| D | CombinerHelper.cpp | 480 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert()
60 getTII().get(TargetOpcode::DBG_VALUE), in buildDirectDbgValue()
73 getTII().get(TargetOpcode::DBG_VALUE), in buildIndirectDbgValue()
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| D | CombinerHelper.cpp | 478 Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT in applyCombineExtendingLoads()
1754 MI.setDesc(MIB.getTII().get(TargetOpcode::G_SHL)); in applyCombineMulToShl()
2524 return Builder.getTII().produceSameValue(*I1, *I2, &MRI); in matchEqualDefs()
3046 Def->setDesc(Builder.getTII().get(TargetOpcode::G_OR)); in applyNotCmp()
3049 Def->setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyNotCmp()
3099 MI.setDesc(Builder.getTII().get(TargetOpcode::G_AND)); in applyXorOfAndWithSameReg()
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| D | LegalizerHelper.cpp | 608 isLibCallInTailPosition(MIRBuilder.getTII(), MI); in createMemLibcall()
2311 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); in widenScalar()
2844 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); in changeOpcode()
2890 const auto &TII = MIRBuilder.getTII(); in lower()
4833 const auto &TII = MIRBuilder.getTII(); in lowerBitCount()
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsLegalizerInfo.cpp | 472 .constrainAllUses(MIRBuilder.getTII(), *ST.getRegisterInfo(), in SelectMSA3OpIntrinsic()
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| D | MipsCallLowering.cpp | 604 MIB.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(), in lowerCall()
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RDFGraph.h | 662 const TargetInstrInfo &getTII() const { return TII; } in getTII() function
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 247 const TargetInstrInfo &getTII() { in getTII() function
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| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 259 const TargetInstrInfo &getTII() { in getTII() function
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1788 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
2701 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue()
4099 MI.setDesc(B.getTII().get(NewOpcode)); in legalizeImageIntrinsic()
4444 MI.setDesc(B.getTII().get(AMDGPU::G_AMDGPU_S_BUFFER_LOAD)); in legalizeSBufferLoad()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RDFGraph.cpp | 227 OS << Print<NodeId>(P.Obj.Id, P.G) << ": " << P.G.getTII().getName(Opc); in operator <<()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1275 MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST)); in legalizeAddrSpaceCast()
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