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Searched refs:hasSVE (Results 1 – 14 of 14) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenFastISel.inc619 if ((Subtarget->hasSVE())) {
626 if ((Subtarget->hasSVE())) {
633 if ((Subtarget->hasSVE())) {
662 if ((Subtarget->hasSVE())) {
1257 if ((Subtarget->hasSVE())) {
1266 if ((Subtarget->hasSVE())) {
1275 if ((Subtarget->hasSVE())) {
1284 if ((Subtarget->hasSVE())) {
1293 if ((Subtarget->hasSVE())) {
1302 if ((Subtarget->hasSVE())) {
[all …]
DAArch64GenGlobalISel.inc96 if (Subtarget->hasSVE())
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.h105 if (ST->hasSVE()) in getRegisterBitWidth()
171 if (!isa<ScalableVectorType>(DataType) || !ST->hasSVE()) in isLegalMaskedLoadStore()
DAArch64Subtarget.cpp375 return hasSVE() && getMinSVEVectorSizeInBits() >= 256; in useSVEForFixedLengthVectors()
DAArch64RegisterInfo.cpp387 if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) { in hasBasePointer()
436 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() || in useFPForScavengingIndex()
DAArch64Subtarget.h428 bool hasSVE() const { return HasSVE; } in hasSVE() function
DAArch64InstrInfo.cpp2829 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()
2840 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()
3161 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3205 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3227 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3238 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3249 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3315 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()
3359 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()
3381 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()
[all …]
DAArch64ISelLowering.cpp256 if (Subtarget->hasSVE()) { in AArch64TargetLowering()
1057 if (Subtarget->hasSVE()) in AArch64TargetLowering()
1063 if (Subtarget->hasSVE()) { in AArch64TargetLowering()
DAArch64InstrInfo.td110 def HasSVE : Predicate<"Subtarget->hasSVE()">,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64TargetTransformInfo.h153 if (!isa<VectorType>(DataType) || !ST->hasSVE()) in isLegalMaskedLoadStore()
DAArch64Subtarget.h384 bool hasSVE() const { return HasSVE; } in hasSVE() function
DAArch64InstrInfo.cpp2564 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()
2575 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()
2941 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
2945 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()
3084 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()
3088 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()
DAArch64ISelLowering.cpp166 if (Subtarget->hasSVE()) { in AArch64TargetLowering()
853 if (Subtarget->hasSVE()) { in AArch64TargetLowering()
DAArch64InstrInfo.td111 def HasSVE : Predicate<"Subtarget->hasSVE()">,